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Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup

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Remove passes redundant with opt_dff
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clairexen 2020-08-20 16:21:58 +02:00 • committed by GitHub
commit 6a68b8ed54
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11 changed files with 129 additions and 1661 deletions
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50
tests/techmap/dff2dffs.ys
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@ -1,50 +0,0 @@
read_verilog << EOT
module top(...);
input clk;
input d;
input sr;
output reg q0, q1, q2, q3, q4, q5;
initial q0 = 1'b0;
initial q1 = 1'b0;
initial q2 = 1'b1;
initial q3 = 1'b1;
initial q4 = 1'bx;
initial q5 = 1'bx;
always @(posedge clk) begin
q0 <= sr ? 1'b0 : d;
q1 <= sr ? 1'b1 : d;
q2 <= sr ? 1'b0 : d;
q3 <= sr ? 1'b1 : d;
q4 <= sr ? 1'b0 : d;
q5 <= sr ? 1'b1 : d;
end
endmodule
EOT
proc
simplemap
design -save ref
dff2dffs
clean
select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i
select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i
select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
design -load ref
dff2dffs -match-init
clean
select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i
select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i
select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i