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Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup
Remove passes redundant with opt_dff
This commit is contained in:
clairexen
GitHub
commit
6a68b8ed54
11 changed files with 129 additions and 1661 deletions
129
tests/opt/opt_dff_dffmux.ys
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129
tests/opt/opt_dff_dffmux.ys
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@ -0,0 +1,129 @@
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 0 t:$dffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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wreduce
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 0 t:$dffe %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 0 t:$dffe %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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select -assert-count 1 t:$dffe r:WIDTH=4 %i
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select -assert-count 0 t:$dffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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wreduce
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select -assert-count 1 t:$sdffe r:WIDTH=2 %i
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select -assert-count 0 t:$sdffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) begin
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if (ce) o <= i;
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if (!rstn) o <= 4'b1111;
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end
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endmodule
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EOT
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proc
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equiv_opt -assert opt
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design -load postopt
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wreduce
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select -assert-count 1 t:$sdffe r:WIDTH=2 %i
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select -assert-count 0 t:$sdffe %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module opt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
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initial o <= 4'b0010;
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always @(posedge clk) begin
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if (ce) o <= i;
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if (!rstn) o <= 4'b1111;
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end
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endmodule
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EOT
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proc
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# NB: equiv_opt uses equiv_induct which covers
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# only the induction half of temporal induction
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# --- missing the base-case half
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# This makes it akin to `sat -tempinduct-inductonly`
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# instead of `sat -tempinduct-baseonly` or
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# `sat -tempinduct` which is necessary for this
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# testcase
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#equiv_opt -assert opt
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design -save gold
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opt
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wreduce
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -tempinduct -verify -prove-asserts -show-ports miter
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design -load gate
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select -assert-count 1 t:$sdffe r:WIDTH=3 %i
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select -assert-count 0 t:$sdffe %% t:* %D
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@ -1,50 +0,0 @@
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read_verilog << EOT
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module top(...);
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input clk;
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input d;
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input sr;
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output reg q0, q1, q2, q3, q4, q5;
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initial q0 = 1'b0;
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initial q1 = 1'b0;
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initial q2 = 1'b1;
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initial q3 = 1'b1;
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initial q4 = 1'bx;
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initial q5 = 1'bx;
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always @(posedge clk) begin
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q0 <= sr ? 1'b0 : d;
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q1 <= sr ? 1'b1 : d;
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q2 <= sr ? 1'b0 : d;
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q3 <= sr ? 1'b1 : d;
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q4 <= sr ? 1'b0 : d;
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q5 <= sr ? 1'b1 : d;
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end
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endmodule
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EOT
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proc
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simplemap
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design -save ref
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dff2dffs
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clean
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select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
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design -load ref
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dff2dffs -match-init
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clean
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select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
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select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i
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select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
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@ -68,146 +68,3 @@ equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 0 t:*
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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###################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
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always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=4 %i
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select -assert-count 1 t:$mux r:WIDTH=4 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o);
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always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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wreduce
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 2 t:$mux
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select -assert-count 2 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) begin
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if (ce) o <= i;
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if (!rstn) o <= 4'b1111;
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end
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endmodule
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EOT
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proc
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equiv_opt -assert peepopt
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design -load postopt
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wreduce
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 2 t:$mux
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select -assert-count 2 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
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initial o <= 4'b0010;
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always @(posedge clk) begin
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if (ce) o <= i;
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if (!rstn) o <= 4'b1111;
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end
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endmodule
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EOT
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proc
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# NB: equiv_opt uses equiv_induct which covers
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# only the induction half of temporal induction
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# --- missing the base-case half
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# This makes it akin to `sat -tempinduct-inductonly`
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# instead of `sat -tempinduct-baseonly` or
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# `sat -tempinduct` which is necessary for this
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# testcase
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#equiv_opt -assert peepopt
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design -save gold
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peepopt
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wreduce
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -tempinduct -verify -prove-asserts -show-ports miter
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design -load gate
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select -assert-count 1 t:$dff r:WIDTH=4 %i
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select -assert-count 2 t:$mux
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select -assert-count 2 t:$mux r:WIDTH=4 %i
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select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
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