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write_xaiger to support non-bit cell connections, and cope with COs for -O

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This commit is contained in:
Eddie Hung 2019-02-16 21:00:39 -08:00
parent f853b2f3c1
commit 6a57de9013
1 changed files with 15 additions and 13 deletions
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8
backends/aiger/xaiger.cc
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@ -206,8 +206,9 @@ struct XAigerWriter
for (const auto &c : cell->connections()) { for (const auto &c : cell->connections()) {
if (c.second.is_fully_const()) continue; if (c.second.is_fully_const()) continue;
SigBit b = c.second.as_bit(); for (auto b : c.second.bits()) {
Wire *w = b.wire; Wire *w = b.wire;
if (!w) continue;
if (cell->input(c.first)) { if (cell->input(c.first)) {
SigBit I = sigmap(b); SigBit I = sigmap(b);
if (!w->port_input) if (!w->port_input)
@ -218,6 +219,7 @@ struct XAigerWriter
ci_bits.insert(O); ci_bits.insert(O);
} }
else log_abort(); else log_abort();
}
if (!type_map.count(cell->type)) if (!type_map.count(cell->type))
type_map[cell->type] = type_map.size()+1; type_map[cell->type] = type_map.size()+1;
} }
@ -343,7 +345,7 @@ struct XAigerWriter
aig_outputs.push_back(bit2aig(bit)); aig_outputs.push_back(bit2aig(bit));
} }
if (omode && output_bits.empty()) { if (omode && output_bits.empty() && co_bits.empty()) {
aig_o++; aig_o++;
aig_outputs.push_back(0); aig_outputs.push_back(0);
} }
@ -564,7 +566,7 @@ struct XAigerWriter
output_lines.sort(); output_lines.sort();
for (auto &it : output_lines) for (auto &it : output_lines)
f << it.second; f << it.second;
if (omode && output_bits.empty()) { if (omode && output_bits.empty() && co_bits.empty()) {
f << "output 0 0 __dummy_o__\n"; f << "output 0 0 __dummy_o__\n";
} }