From 6a45e7b29086f9c285f17a1248fa4ee5e410c953 Mon Sep 17 00:00:00 2001 From: nella Date: Thu, 25 Jun 2026 11:14:54 +0200 Subject: [PATCH] Add tests. --- tests/proc/rmdead_case_x.ys | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 tests/proc/rmdead_case_x.ys diff --git a/tests/proc/rmdead_case_x.ys b/tests/proc/rmdead_case_x.ys new file mode 100644 index 000000000..6a44ec462 --- /dev/null +++ b/tests/proc/rmdead_case_x.ys @@ -0,0 +1,40 @@ +# https://github.com/YosysHQ/yosys/issues/5979 + +read_verilog -sv << EOF +module top ( + input wire [1:0] sel, + input wire [3:0] a, + input wire [3:0] b, + output reg [3:0] y +); + always @* begin + case (sel) + 2'b1x: y = a; + 2'b10: y = b; + default: y = a; + endcase + end +endmodule + +module gold ( + input wire [1:0] sel, + input wire [3:0] a, + input wire [3:0] b, + output reg [3:0] y +); + always @* begin + if (sel == 2'b10) y = b; + else y = a; + end +endmodule +EOF + +proc +opt -full + +select -assert-count 1 top/o:y %ci* top/i:b %i + +equiv_make gold top equiv +cd equiv +equiv_simple +equiv_status -assert