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Updates from yosys

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This commit is contained in:
Akash Levy 2024-04-14 18:53:44 -07:00
parent 45eee94a8f
commit 6a3bb58d5d
10 changed files with 209 additions and 36 deletions
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2
passes/memory/memory_map.cc
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@ -415,7 +415,7 @@ struct MemoryMapPass : public Pass {
log(" to any of the values.\n");
log("\n");
log(" -iattr\n");
log(" for -attr, ignore case of <value>.\n");
log(" for -attr, suppress case sensitivity in matching of <value>.\n");
log("\n");
log(" -rom-only\n");
log(" only perform conversion for ROMs (memories with no write ports).\n");

7
passes/opt/opt_clean.cc
View file

@ -443,13 +443,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (!raw_used_signals.check_any(s1)) {
// delete wires that aren't used by anything directly
goto delete_this_wire;
} else
if (!used_signals.check_any(s2)) {
// this path shouldn't be possible: this wire is used directly (otherwise it would get cleaned up above), and indirectly
// used wires are a superset of those used directly
log_assert(false);
// delete wires that aren't used by anything indirectly, even though other wires may alias it
goto delete_this_wire;
}
if (0)

2
passes/opt/opt_demorgan.cc
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@ -183,7 +183,7 @@ struct OptDemorganPass : public Pass {
{
log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
int argidx = 0;
int argidx = 1;
extra_args(args, argidx, design);
unsigned int cells_changed = 0;