From 21b93ee1fb36c25d240ea1146c3f4b7d9239881c Mon Sep 17 00:00:00 2001
From: clemens <cwalter@ethz.ch>
Date: Tue, 15 Apr 2025 09:38:04 +0200
Subject: [PATCH 1/3] fix sequential area not being included in
 addition/multiplication Fixes a bug where the sequential area isn't part of
 the Stat_numeric_members that are used to automatically add/mul the
 statdata_t members.

---
 passes/cmds/stat.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 7e51b6cb1..d68eda70a 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -40,7 +40,7 @@ struct statdata_t
 			X(num_ports) X(num_port_bits) X(num_memories) X(num_memory_bits) X(num_cells) \
 			X(num_processes)
 
-	#define STAT_NUMERIC_MEMBERS STAT_INT_MEMBERS X(area)
+	#define STAT_NUMERIC_MEMBERS STAT_INT_MEMBERS X(area) X(sequential_area)
 
 	#define X(_name) unsigned int _name;
 	STAT_INT_MEMBERS

From 01d80c74038dfb727e2ee19af53b813c4de364ef Mon Sep 17 00:00:00 2001
From: clemens <cwalter@ethz.ch>
Date: Sat, 19 Apr 2025 20:41:10 +0200
Subject: [PATCH 2/3] add testcase

---
 tests/various/stat.ys | 49 +++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/tests/various/stat.ys b/tests/various/stat.ys
index ad96fe8d4..7c8700494 100644
--- a/tests/various/stat.ys
+++ b/tests/various/stat.ys
@@ -1,4 +1,4 @@
-read_rtlil << EOF
+read_rtlil << EOT
 module \top
   wire input 1 \A
   wire output 2 \Y
@@ -8,7 +8,52 @@ module \top
     connect \Y \Y
   end
 end
-EOF
+EOT
 logger -expect log "Chip area for module '\\top': 9.072000" 1
 logger -expect-no-warnings
 stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
+
+
+design -reset
+read_rtlil <<EOT
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  wire output 3 \NY
+  cell \child \sequential
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \NY \NY
+  end
+
+  cell \sg13g2_and2_1 \sub
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+
+module \child
+  wire input 1 \A
+  wire input 2 \B
+  wire input 3 \R
+
+  wire output 4 \Y
+  wire output 5 \NY
+  cell \sg13g2_dfrbp_1 
+    connect \CLK \A
+    connect \D \B
+    connect \Q \Y
+    connect \Q_N \NY
+    connect \RESET_B \R
+  end
+
+  
+end
+EOT
+logger -expect log "Chip area for module '\\top': 63.504000" 1
+logger -expect log "of which used for sequential elements: 54.432000 (85.71%) " 1
+logger -expect-no-warnings
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz

From 41375a5f057d230892d0b39e4d4787eb1d72f493 Mon Sep 17 00:00:00 2001
From: cwalter <cwalter@ethz.ch>
Date: Sun, 20 Apr 2025 16:44:22 +0200
Subject: [PATCH 3/3] create testcase to check correct addition of areas.

---
 tests/various/stat.ys | 37 ++++++++++++++++++++++++++-----------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/tests/various/stat.ys b/tests/various/stat.ys
index 7c8700494..cf084a986 100644
--- a/tests/various/stat.ys
+++ b/tests/various/stat.ys
@@ -15,20 +15,35 @@ stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.
 
 
 design -reset
-read_rtlil <<EOT
+read_rtlil << EOT
 module \top
   wire input 1 \A
   wire output 2 \Y
-  wire output 3 \NY
+  wire output 3 \N
+
+  cell \sg13g2_and2_1 \sub1
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+
   cell \child \sequential
     connect \A \A
     connect \B 1'0
     connect \R 1'0
     connect \Y \Y
-    connect \NY \NY
+    connect \N \N
   end
 
-  cell \sg13g2_and2_1 \sub
+  cell \child \sequential1
+    connect \A \A
+    connect \B 1'0
+    connect \R 1'0
+    connect \Y \Y
+    connect \N \N
+  end
+
+  cell \sg13g2_and2_1 \sub2
     connect \A \A
     connect \B 1'0
     connect \Y \Y
@@ -41,19 +56,19 @@ module \child
   wire input 3 \R
 
   wire output 4 \Y
-  wire output 5 \NY
-  cell \sg13g2_dfrbp_1 
+  wire output 5 \N
+
+  cell \sg13g2_dfrbp_1 \sequential_ff
     connect \CLK \A
     connect \D \B
     connect \Q \Y
-    connect \Q_N \NY
+    connect \Q_N \N
     connect \RESET_B \R
   end
 
-  
 end
 EOT
-logger -expect log "Chip area for module '\\top': 63.504000" 1
-logger -expect log "of which used for sequential elements: 54.432000 (85.71%) " 1
+logger -expect log "Chip area for top module '\\top': 112.492800" 1
+logger -expect log "of which used for sequential elements: 94.348800" 1
 logger -expect-no-warnings
-stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top