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xilinx_dsp: another typo; move xilinx specific test

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This commit is contained in:
Eddie Hung 2020-01-17 17:07:03 -08:00
parent db68e4c2a7
commit 6a163b5ddd
2 changed files with 1 additions and 1 deletions
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11
tests/various/bug1462.ys
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@ -1,11 +0,0 @@
read_verilog << EOF
module top(...);
input wire [31:0] A;
output wire [31:0] P;
assign P = A * 32'h12300000;
endmodule
EOF
synth_xilinx