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dlatchlibmap: making a copy of test files dfflibmap* to dlatchlibmap*
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Iztok Jeras
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268
tests/techmap/dlatchlibmap_formal.ys
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268
tests/techmap/dlatchlibmap_formal.ys
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##################################################################
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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assume property (~R || ~S);
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffsr_s.lib
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffsr_s.lib top
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clk2fflogic
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flatten
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opt_clean -purge
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miter -equiv -make_assert -flatten top_unmapped top miter
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hierarchy -top miter
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# Prove that this is equivalent with the assumption
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sat -verify -prove-asserts -set-assumes -enable_undef -set-init-undef -show-public -seq 3 miter
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# Prove that this is NOT equivalent WITHOUT the assumption
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sat -falsify -prove-asserts -enable_undef -set-init-undef -seq 3 miter
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##################################################################
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design -reset
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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assume property (~R || ~S);
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffsr_r.lib
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffsr_r.lib top
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clk2fflogic
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flatten
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opt_clean -purge
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miter -equiv -make_assert -flatten top_unmapped top miter
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hierarchy -top miter
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# Prove that this is equivalent with the assumption
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sat -verify -prove-asserts -set-assumes -enable_undef -set-init-undef -show-public -seq 3 miter
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# Prove that this is NOT equivalent WITHOUT the assumption
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sat -falsify -prove-asserts -enable_undef -set-init-undef -seq 3 miter
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##################################################################
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design -reset
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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// no assume when mapping to X
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffsr_x.lib
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opt
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffsr_x.lib top
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clk2fflogic
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flatten
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opt_clean -purge
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miter -equiv -make_assert -flatten top_unmapped top miter
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hierarchy -top miter
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# Prove that this is equivalent
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sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
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##################################################################
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design -reset
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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// Formal checking of directly instantiated DFFSR doesn't work at the moment
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// likely due to an equiv_induct -set-assumes assume bug #5196
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// no assume when mapping to unset clear_preset_var
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffn_dffe.lib
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read_liberty dfflibmap_dffsr_not_next.lib
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
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clk2fflogic
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flatten
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opt_clean -purge
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miter -equiv -make_assert -flatten top_unmapped top miter
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hierarchy -top miter
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# Prove that this is equivalent
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sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
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##################################################################
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design -reset
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read_verilog -sv -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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assume property (~R || ~S);
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffsr_not_next_l.lib
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copy top top_unmapped
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dfflibmap -liberty dfflibmap_dffsr_not_next_l.lib top
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clk2fflogic
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flatten
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opt_clean -purge
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miter -equiv -make_assert -flatten top_unmapped top miter
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hierarchy -top miter
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# Prove that this is equivalent with the assumption
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sat -verify -prove-asserts -set-assumes -enable_undef -set-init-undef -show-public -seq 3 miter
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# Prove that this is NOT equivalent WITHOUT the assumption
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sat -falsify -prove-asserts -enable_undef -set-init-undef -seq 3 miter
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##################################################################
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design -reset
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read_verilog <<EOT
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module top(input C, D, E, S, R, output Q);
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// DFFSR with priority R over S
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always @(posedge C, posedge R, posedge S)
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if (R == 1)
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Q <= 0;
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else if (S == 1)
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Q <= 1;
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else
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Q <= D;
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffn_dffe.lib
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read_liberty dfflibmap_dffsr_not_next.lib
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copy top top_unmapped
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simplemap top
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dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
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clk2fflogic
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct -set-assumes equiv
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equiv_status -assert equiv
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##################################################################
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design -reset
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read_verilog <<EOT
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module top(input C, D, R, output Q);
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// DFF with preset
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always @(posedge C or negedge R) begin
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if (!R) Q <= 1'b1;
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else Q <= D;
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end
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endmodule
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EOT
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proc
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opt
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read_liberty dfflibmap_dffn_dffe.lib
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read_liberty dfflibmap_dff_not_next.lib
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copy top top_unmapped
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simplemap top
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dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dff_not_next.lib top
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clk2fflogic
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flatten
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opt_clean -purge
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equiv_make top top_unmapped equiv
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equiv_induct -set-assumes equiv
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equiv_status -assert equiv
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