mirror of
https://github.com/YosysHQ/yosys
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dlatchlibmap: making a copy of test files dfflibmap* to dlatchlibmap*
This commit is contained in:
Iztok Jeras
parent
6b1d5dedbf
commit
69df81756c
13 changed files with 843 additions and 0 deletions
31
tests/techmap/dlatchlibmap-sim.v
Normal file
31
tests/techmap/dlatchlibmap-sim.v
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module dffn(input CLK, D, output reg Q, output QN);
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always @(negedge CLK)
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Q <= D;
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assign QN = ~Q;
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endmodule
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module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
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always @(posedge CLK, posedge CLEAR, posedge PRESET)
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if (CLEAR)
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Q <= 0;
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else if (PRESET)
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Q <= 1;
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else
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Q <= D;
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assign QN = ~Q;
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endmodule
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module dffe(input CLK, EN, D, output reg Q, output QN);
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always @(negedge CLK)
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if (EN) Q <= D;
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assign QN = ~Q;
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endmodule
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79
tests/techmap/dlatchlibmap.lib
Normal file
79
tests/techmap/dlatchlibmap.lib
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@ -0,0 +1,79 @@
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library(test) {
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/* D-type flip-flop with asynchronous reset and preset */
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cell (dffn) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "D";
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clocked_on : "!CLK";
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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cell (dffsr) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "D";
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clocked_on : "CLK";
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clear : "CLEAR";
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preset : "PRESET";
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clear_preset_var1 : L;
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clear_preset_var2 : L;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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cell (dffe) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "(D EN) | (IQ !EN)";
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clocked_on : "!CLK";
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}
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pin(D) {
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direction : input;
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}
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pin(EN) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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99
tests/techmap/dlatchlibmap.ys
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99
tests/techmap/dlatchlibmap.ys
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@ -0,0 +1,99 @@
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read_verilog -icells <<EOT
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module top(input C, D, E, S, R, output [11:0] Q);
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$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
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$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
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$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
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$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
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$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4]));
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$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
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assign Q[11:6] = ~Q[5:0];
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endmodule
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EOT
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simplemap
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design -save orig
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read_liberty -lib dfflibmap.lib
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equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib
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equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib
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dfflibmap -prepare -liberty dfflibmap.lib
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equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib
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design -load orig
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dfflibmap -liberty dfflibmap.lib
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clean
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select -assert-count 5 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr
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select -assert-count 1 t:dffe
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select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -prepare -liberty dfflibmap.lib
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select -assert-count 11 t:$_NOT_
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select -assert-count 1 t:$_DFF_N_
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select -assert-count 4 t:$_DFFSR_PPP_
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select -assert-count 1 t:$_DFFE_NP_
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select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_DFFE_NP_ t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -map-only -liberty dfflibmap.lib
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select -assert-count 6 t:$_NOT_
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select -assert-count 0 t:dffn
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select -assert-count 1 t:dffsr
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design -load orig
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dfflibmap -prepare -liberty dfflibmap.lib
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dfflibmap -map-only -liberty dfflibmap.lib
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clean
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select -assert-count 5 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr
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select -assert-count 1 t:dffe
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select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -prepare -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_r.lib
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dfflibmap -map-only -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_r.lib
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clean
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select -assert-count 5 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 1 t:dffe
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select -assert-count 4 t:dffsr
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select -assert-none t:dffn t:dffsr t:dffe t:$_NOT_ %% %n t:* %i
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design -load orig
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dfflibmap -liberty dfflibmap.lib -dont_use *ffn
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clean
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select -assert-count 0 t:dffn
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select -assert-count 5 t:dffsr
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select -assert-count 1 t:dffe
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design -load orig
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dfflibmap -liberty dfflibmap.lib -liberty dfflibmap_dffsr_mixedpol.lib -dont_use dffsr
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clean
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# We have one more _NOT_ than with the regular dffsr
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select -assert-count 6 t:$_NOT_
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select -assert-count 1 t:dffn
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select -assert-count 4 t:dffsr_mixedpol
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select -assert-count 1 t:dffe
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# The additional NOT is on ff2.
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# Originally, ff2.R is an active high "set".
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# dffsr_mixedpol has functionally swapped labels due to the next_state inversion,
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# so we use its CLEAR port for the "set",
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# but we have to invert it because the CLEAR pin is active low.
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# ff2.CLEAR = !R
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select -assert-count 1 c:ff2 %x:+[CLEAR] %ci t:$_NOT_ %i
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24
tests/techmap/dlatchlibmap_dlatch_not_data.lib
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24
tests/techmap/dlatchlibmap_dlatch_not_data.lib
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library (test_not_next) {
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cell (dff_not_next) {
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area: 1.0;
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pin (QN) {
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direction : output;
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function : "STATE";
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}
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pin (CLK) {
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direction : input;
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clock : true;
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}
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pin (D) {
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direction : input;
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}
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pin (RN) {
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direction : input;
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}
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ff (STATE, STATEN) {
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clocked_on: "CLK";
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next_state: "!D";
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preset : "!RN";
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}
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}
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}
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47
tests/techmap/dlatchlibmap_dlatchn.lib
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47
tests/techmap/dlatchlibmap_dlatchn.lib
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library(test) {
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cell (dffn) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "D";
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clocked_on : "!CLK";
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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cell (dffe) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "(D&EN) | (IQ&!EN)";
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clocked_on : "!CLK";
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}
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pin(D) {
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direction : input;
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}
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pin(EN) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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35
tests/techmap/dlatchlibmap_dlatchsr_mixedpol.lib
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35
tests/techmap/dlatchlibmap_dlatchsr_mixedpol.lib
Normal file
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@ -0,0 +1,35 @@
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library(test) {
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cell (dffsr_mixedpol) {
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area : 6;
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ff("IQ", "IQN") {
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// look here
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next_state : "!D";
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clocked_on : "CLK";
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// look here
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clear : "!CLEAR";
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preset : "PRESET";
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clear_preset_var1 : L;
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clear_preset_var2 : L;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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28
tests/techmap/dlatchlibmap_dlatchsr_not_data.lib
Normal file
28
tests/techmap/dlatchlibmap_dlatchsr_not_data.lib
Normal file
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@ -0,0 +1,28 @@
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library (test_not_next) {
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cell (dffsr_not_next) {
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area : 1.0;
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pin (Q) {
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direction : output;
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function : "STATE";
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}
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pin (CLK) {
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clock : true;
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direction : input;
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}
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pin (D) {
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direction : input;
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}
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pin (RN) {
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direction : input;
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}
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pin (SN) {
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direction : input;
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}
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ff (STATE,STATEN) {
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clear : "!SN";
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clocked_on : "CLK";
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next_state : "!D";
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preset : "!RN";
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}
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}
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}
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33
tests/techmap/dlatchlibmap_dlatchsr_not_data_l.lib
Normal file
33
tests/techmap/dlatchlibmap_dlatchsr_not_data_l.lib
Normal file
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@ -0,0 +1,33 @@
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library(test) {
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cell (dffr_not_next) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "!D";
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clocked_on : "CLK";
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clear : "CLEAR";
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preset : "PRESET";
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clear_preset_var1 : L;
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clear_preset_var2 : L;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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33
tests/techmap/dlatchlibmap_dlatchsr_r.lib
Normal file
33
tests/techmap/dlatchlibmap_dlatchsr_r.lib
Normal file
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@ -0,0 +1,33 @@
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library(test) {
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cell (dffsr) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "D";
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clocked_on : "CLK";
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clear : "CLEAR";
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preset : "PRESET";
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clear_preset_var1 : L;
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clear_preset_var2 : H;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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33
tests/techmap/dlatchlibmap_dlatchsr_s.lib
Normal file
33
tests/techmap/dlatchlibmap_dlatchsr_s.lib
Normal file
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@ -0,0 +1,33 @@
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library(test) {
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cell (dffsr) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "D";
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clocked_on : "CLK";
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clear : "CLEAR";
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preset : "PRESET";
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clear_preset_var1 : H;
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clear_preset_var2 : L;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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33
tests/techmap/dlatchlibmap_dlatchsr_x.lib
Normal file
33
tests/techmap/dlatchlibmap_dlatchsr_x.lib
Normal file
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library(test) {
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cell (dffsr) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "D";
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clocked_on : "CLK";
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clear : "CLEAR";
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preset : "PRESET";
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clear_preset_var1 : X;
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clear_preset_var2 : X;
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}
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pin(D) {
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direction : input;
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}
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pin(CLK) {
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direction : input;
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}
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pin(CLEAR) {
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direction : input;
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}
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pin(PRESET) {
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direction : input;
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}
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pin(Q) {
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direction: output;
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function : "IQ";
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}
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pin(QN) {
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direction: output;
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function : "IQN";
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}
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}
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}
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268
tests/techmap/dlatchlibmap_formal.ys
Normal file
268
tests/techmap/dlatchlibmap_formal.ys
Normal file
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@ -0,0 +1,268 @@
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##################################################################
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read_verilog -sv -icells <<EOT
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||||
|
||||
module top(input C, D, E, S, R, output [11:0] Q);
|
||||
|
||||
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
|
||||
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
|
||||
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
|
||||
|
||||
assume property (~R || ~S);
|
||||
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
|
||||
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
|
||||
|
||||
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
|
||||
|
||||
assign Q[11:6] = ~Q[5:0];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffsr_s.lib
|
||||
|
||||
copy top top_unmapped
|
||||
dfflibmap -liberty dfflibmap_dffsr_s.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
hierarchy -top miter
|
||||
# Prove that this is equivalent with the assumption
|
||||
sat -verify -prove-asserts -set-assumes -enable_undef -set-init-undef -show-public -seq 3 miter
|
||||
# Prove that this is NOT equivalent WITHOUT the assumption
|
||||
sat -falsify -prove-asserts -enable_undef -set-init-undef -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
design -reset
|
||||
read_verilog -sv -icells <<EOT
|
||||
|
||||
module top(input C, D, E, S, R, output [11:0] Q);
|
||||
|
||||
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
|
||||
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
|
||||
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
|
||||
|
||||
assume property (~R || ~S);
|
||||
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
|
||||
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
|
||||
|
||||
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
|
||||
|
||||
assign Q[11:6] = ~Q[5:0];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffsr_r.lib
|
||||
|
||||
copy top top_unmapped
|
||||
dfflibmap -liberty dfflibmap_dffsr_r.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
hierarchy -top miter
|
||||
# Prove that this is equivalent with the assumption
|
||||
sat -verify -prove-asserts -set-assumes -enable_undef -set-init-undef -show-public -seq 3 miter
|
||||
# Prove that this is NOT equivalent WITHOUT the assumption
|
||||
sat -falsify -prove-asserts -enable_undef -set-init-undef -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
design -reset
|
||||
read_verilog -sv -icells <<EOT
|
||||
|
||||
module top(input C, D, E, S, R, output [11:0] Q);
|
||||
|
||||
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
|
||||
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
|
||||
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
|
||||
|
||||
// no assume when mapping to X
|
||||
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
|
||||
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
|
||||
|
||||
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
|
||||
|
||||
assign Q[11:6] = ~Q[5:0];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffsr_x.lib
|
||||
opt
|
||||
|
||||
copy top top_unmapped
|
||||
dfflibmap -liberty dfflibmap_dffsr_x.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
hierarchy -top miter
|
||||
|
||||
# Prove that this is equivalent
|
||||
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
design -reset
|
||||
read_verilog -sv -icells <<EOT
|
||||
|
||||
module top(input C, D, E, S, R, output [11:0] Q);
|
||||
|
||||
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
|
||||
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
|
||||
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
|
||||
|
||||
// Formal checking of directly instantiated DFFSR doesn't work at the moment
|
||||
// likely due to an equiv_induct -set-assumes assume bug #5196
|
||||
|
||||
// no assume when mapping to unset clear_preset_var
|
||||
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
|
||||
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
|
||||
|
||||
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
|
||||
|
||||
assign Q[11:6] = ~Q[5:0];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffn_dffe.lib
|
||||
read_liberty dfflibmap_dffsr_not_next.lib
|
||||
|
||||
copy top top_unmapped
|
||||
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
hierarchy -top miter
|
||||
|
||||
# Prove that this is equivalent
|
||||
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
design -reset
|
||||
read_verilog -sv -icells <<EOT
|
||||
|
||||
module top(input C, D, E, S, R, output [11:0] Q);
|
||||
|
||||
$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
|
||||
$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
|
||||
$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
|
||||
|
||||
assume property (~R || ~S);
|
||||
$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3]));
|
||||
$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(~R), .S(~S), .Q(Q[4]));
|
||||
|
||||
$_DFFE_PP_ ff5 (.C(C), .D(D), .E(E), .Q(Q[5]));
|
||||
|
||||
assign Q[11:6] = ~Q[5:0];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffsr_not_next_l.lib
|
||||
|
||||
copy top top_unmapped
|
||||
dfflibmap -liberty dfflibmap_dffsr_not_next_l.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
hierarchy -top miter
|
||||
|
||||
# Prove that this is equivalent with the assumption
|
||||
sat -verify -prove-asserts -set-assumes -enable_undef -set-init-undef -show-public -seq 3 miter
|
||||
# Prove that this is NOT equivalent WITHOUT the assumption
|
||||
sat -falsify -prove-asserts -enable_undef -set-init-undef -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
|
||||
module top(input C, D, E, S, R, output Q);
|
||||
// DFFSR with priority R over S
|
||||
always @(posedge C, posedge R, posedge S)
|
||||
if (R == 1)
|
||||
Q <= 0;
|
||||
else if (S == 1)
|
||||
Q <= 1;
|
||||
else
|
||||
Q <= D;
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffn_dffe.lib
|
||||
read_liberty dfflibmap_dffsr_not_next.lib
|
||||
|
||||
copy top top_unmapped
|
||||
simplemap top
|
||||
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
equiv_make top top_unmapped equiv
|
||||
equiv_induct -set-assumes equiv
|
||||
equiv_status -assert equiv
|
||||
|
||||
##################################################################
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
|
||||
module top(input C, D, R, output Q);
|
||||
// DFF with preset
|
||||
always @(posedge C or negedge R) begin
|
||||
if (!R) Q <= 1'b1;
|
||||
else Q <= D;
|
||||
end
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffn_dffe.lib
|
||||
read_liberty dfflibmap_dff_not_next.lib
|
||||
|
||||
copy top top_unmapped
|
||||
simplemap top
|
||||
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dff_not_next.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
equiv_make top top_unmapped equiv
|
||||
equiv_induct -set-assumes equiv
|
||||
equiv_status -assert equiv
|
||||
100
tests/techmap/dlatchlibmap_proc_formal.ys
Normal file
100
tests/techmap/dlatchlibmap_proc_formal.ys
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
##################################################################
|
||||
|
||||
read_verilog -sv -icells <<EOT
|
||||
|
||||
module top(input C, D, E, S, R, output [7:0] Q);
|
||||
|
||||
always @( posedge C, posedge S, posedge R)
|
||||
if (R)
|
||||
Q[0] <= 0;
|
||||
else if (S)
|
||||
Q[0] <= 1;
|
||||
else
|
||||
Q[0] <= D;
|
||||
|
||||
always @( posedge C, posedge S, posedge R)
|
||||
if (S)
|
||||
Q[1] <= 1;
|
||||
else if (R)
|
||||
Q[1] <= 0;
|
||||
else
|
||||
Q[1] <= D;
|
||||
|
||||
always @( posedge C, posedge S, posedge R)
|
||||
if (R)
|
||||
Q[2] <= 0;
|
||||
else if (S)
|
||||
Q[2] <= 1;
|
||||
else if (E)
|
||||
Q[2] <= D;
|
||||
|
||||
always @( posedge C, posedge S, posedge R)
|
||||
if (S)
|
||||
Q[3] <= 1;
|
||||
else if (R)
|
||||
Q[3] <= 0;
|
||||
else if (E)
|
||||
Q[3] <= D;
|
||||
|
||||
assign Q[7:4] = ~Q[3:0];
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
proc
|
||||
opt
|
||||
read_liberty dfflibmap_dffsr_s.lib
|
||||
|
||||
copy top top_unmapped
|
||||
dfflibmap -liberty dfflibmap_dffsr_s.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
opt_clean -purge
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
|
||||
# Prove that this is equivalent
|
||||
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
delete top miter
|
||||
|
||||
copy top_unmapped top
|
||||
dfflibmap -liberty dfflibmap_dffsr_r.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
|
||||
# Prove that this is equivalent
|
||||
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
delete top miter
|
||||
|
||||
copy top_unmapped top
|
||||
dfflibmap -liberty dfflibmap_dffsr_mixedpol.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
|
||||
# Prove that this is equivalent
|
||||
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
|
||||
|
||||
##################################################################
|
||||
|
||||
delete top miter
|
||||
|
||||
copy top_unmapped top
|
||||
dfflibmap -liberty dfflibmap_dffsr_not_next.lib top
|
||||
|
||||
clk2fflogic
|
||||
flatten
|
||||
miter -equiv -make_assert -flatten top_unmapped top miter
|
||||
|
||||
# Prove that this is equivalent
|
||||
sat -verify -prove-asserts -set-init-undef -show-public -seq 3 miter
|
||||
Loading…
Add table
Add a link
Reference in a new issue