mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Reject wide ports in some passes that will never support them.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2021-05-22 18:18:50 +02:00
parent 35ee774ea8
commit 69bf5c81c7
4 changed files with 35 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

13
backends/btor/btor.cc
View file

@ -728,10 +728,19 @@ struct BtorWorker
log_error("Memory %s.%s has mixed async/sync write ports.\n",
log_id(module), log_id(mem->memid));
for (auto &port : mem->rd_ports)
for (auto &port : mem->rd_ports) {
if (port.clk_enable)
log_error("Memory %s.%s has sync read ports.\n",
log_error("Memory %s.%s has sync read ports. Please use memory_nordff to convert them first.\n",
log_id(module), log_id(mem->memid));
if (port.wide_log2)
log_error("Memory %s.%s has wide read ports. Please use memory_narrow to convert them first.\n",
log_id(module), log_id(mem->memid));
}
for (auto &port : mem->wr_ports) {
if (port.wide_log2)
log_error("Memory %s.%s has wide write ports. Please use memory_narrow to convert them first.\n",
log_id(module), log_id(mem->memid));
}
int data_sid = get_bv_sid(mem->width);
int bool_sid = get_bv_sid(1);