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Use ID() macro in all of passes/opt/
This was obtained by running the following SED command in passes/opt/ and then using "meld foo.cc foo.cc.orig" to manually fix all resulting compiler errors. sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
b5534b66c8
commit
6995914f3f
12 changed files with 991 additions and 991 deletions
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@ -89,8 +89,8 @@ struct ShareWorker
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queue_bits.clear();
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for (auto &pbit : portbits) {
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if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") {
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pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_pool();
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if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) {
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pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID(S))).to_sigbit_pool();
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terminal_bits.insert(bits.begin(), bits.end());
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queue_bits.insert(bits.begin(), bits.end());
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visited_cells.insert(pbit.cell);
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@ -128,7 +128,7 @@ struct ShareWorker
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static int bits_macc(RTLIL::Cell *c)
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{
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Macc m(c);
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int width = GetSize(c->getPort("\\Y"));
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int width = GetSize(c->getPort(ID(Y)));
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return bits_macc(m, width);
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}
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@ -242,7 +242,7 @@ struct ShareWorker
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{
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Macc m1(c1), m2(c2), supermacc;
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int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y"));
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int w1 = GetSize(c1->getPort(ID(Y))), w2 = GetSize(c2->getPort(ID(Y)));
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int width = max(w1, w2);
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m1.optimize(w1);
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@ -328,11 +328,11 @@ struct ShareWorker
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{
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RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width);
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supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort("\\Y")));
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supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort("\\Y")));
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supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID(Y))));
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supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID(Y))));
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supercell->setParam("\\Y_WIDTH", width);
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supercell->setPort("\\Y", sig_y);
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supercell->setParam(ID(Y_WIDTH), width);
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supercell->setPort(ID(Y), sig_y);
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supermacc.optimize(width);
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supermacc.to_cell(supercell);
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@ -368,22 +368,22 @@ struct ShareWorker
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continue;
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}
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if (cell->type == "$memrd") {
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if (cell->parameters.at("\\CLK_ENABLE").as_bool())
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if (cell->type == ID($memrd)) {
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if (cell->parameters.at(ID(CLK_ENABLE)).as_bool())
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continue;
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if (config.opt_aggressive || !modwalker.sigmap(cell->getPort("\\ADDR")).is_fully_const())
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if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID(ADDR))).is_fully_const())
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type.in("$mul", "$div", "$mod")) {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4)
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if (cell->type.in(ID($mul), ID($div), ID($mod))) {
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if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 4)
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8)
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if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
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if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 8)
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shareable_cells.insert(cell);
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continue;
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}
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@ -401,9 +401,9 @@ struct ShareWorker
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if (c1->type != c2->type)
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return false;
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if (c1->type == "$memrd")
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if (c1->type == ID($memrd))
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{
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if (c1->parameters.at("\\MEMID").decode_string() != c2->parameters.at("\\MEMID").decode_string())
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if (c1->parameters.at(ID(MEMID)).decode_string() != c2->parameters.at(ID(MEMID)).decode_string())
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return false;
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return true;
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@ -413,11 +413,11 @@ struct ShareWorker
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{
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if (!config.opt_aggressive)
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{
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
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int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
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int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
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if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
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if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
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@ -426,17 +426,17 @@ struct ShareWorker
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return true;
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}
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if (config.generic_bin_ops.count(c1->type) || c1->type == "$alu")
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if (config.generic_bin_ops.count(c1->type) || c1->type == ID($alu))
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{
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if (!config.opt_aggressive)
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{
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
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int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
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int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
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int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
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int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
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if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
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if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false;
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@ -450,13 +450,13 @@ struct ShareWorker
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{
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if (!config.opt_aggressive)
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{
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
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int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
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int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
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int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
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int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
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int min1_width = min(a1_width, b1_width);
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int max1_width = max(a1_width, b1_width);
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@ -472,7 +472,7 @@ struct ShareWorker
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return true;
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}
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if (c1->type == "$macc")
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if (c1->type == ID($macc))
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{
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if (!config.opt_aggressive)
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if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false;
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@ -510,27 +510,27 @@ struct ShareWorker
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if (config.generic_uni_ops.count(c1->type))
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{
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if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
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{
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RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
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if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
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RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
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RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
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if (unsigned_cell->getPort(ID(A)).to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
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RTLIL::SigSpec new_a = unsigned_cell->getPort(ID(A));
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new_a.append_bit(RTLIL::State::S0);
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unsigned_cell->setPort("\\A", new_a);
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unsigned_cell->setPort(ID(A), new_a);
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}
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unsigned_cell->parameters.at("\\A_SIGNED") = true;
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unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
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unsigned_cell->check();
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}
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bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
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log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
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bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
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log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
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RTLIL::SigSpec a1 = c1->getPort("\\A");
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RTLIL::SigSpec y1 = c1->getPort("\\Y");
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RTLIL::SigSpec a1 = c1->getPort(ID(A));
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RTLIL::SigSpec y1 = c1->getPort(ID(Y));
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RTLIL::SigSpec a2 = c2->getPort("\\A");
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RTLIL::SigSpec y2 = c2->getPort("\\Y");
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RTLIL::SigSpec a2 = c2->getPort(ID(A));
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RTLIL::SigSpec y2 = c2->getPort(ID(Y));
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int a_width = max(a1.size(), a2.size());
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int y_width = max(y1.size(), y2.size());
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@ -544,11 +544,11 @@ struct ShareWorker
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RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
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RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
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supercell->parameters["\\A_SIGNED"] = a_signed;
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supercell->parameters["\\A_WIDTH"] = a_width;
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supercell->parameters["\\Y_WIDTH"] = y_width;
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supercell->setPort("\\A", a);
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supercell->setPort("\\Y", y);
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supercell->parameters[ID(A_SIGNED)] = a_signed;
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supercell->parameters[ID(A_WIDTH)] = a_width;
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supercell->parameters[ID(Y_WIDTH)] = y_width;
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supercell->setPort(ID(A), a);
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supercell->setPort(ID(Y), y);
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supercell_aux.insert(module->addPos(NEW_ID, y, y1));
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supercell_aux.insert(module->addPos(NEW_ID, y, y2));
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@ -557,54 +557,54 @@ struct ShareWorker
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return supercell;
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}
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if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == "$alu")
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if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == ID($alu))
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{
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bool modified_src_cells = false;
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if (config.generic_cbin_ops.count(c1->type))
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{
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int score_unflipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) +
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max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int());
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int score_unflipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()) +
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max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int());
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int score_flipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) +
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max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int());
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int score_flipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()) +
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max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int());
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if (score_flipped < score_unflipped)
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{
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RTLIL::SigSpec tmp = c2->getPort("\\A");
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c2->setPort("\\A", c2->getPort("\\B"));
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c2->setPort("\\B", tmp);
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RTLIL::SigSpec tmp = c2->getPort(ID(A));
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c2->setPort(ID(A), c2->getPort(ID(B)));
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c2->setPort(ID(B), tmp);
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std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
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std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
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std::swap(c2->parameters.at(ID(A_WIDTH)), c2->parameters.at(ID(B_WIDTH)));
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std::swap(c2->parameters.at(ID(A_SIGNED)), c2->parameters.at(ID(B_SIGNED)));
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modified_src_cells = true;
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}
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}
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if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
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{
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RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
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if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
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RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
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RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
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if (unsigned_cell->getPort(ID(A)).to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
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RTLIL::SigSpec new_a = unsigned_cell->getPort(ID(A));
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new_a.append_bit(RTLIL::State::S0);
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unsigned_cell->setPort("\\A", new_a);
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unsigned_cell->setPort(ID(A), new_a);
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}
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unsigned_cell->parameters.at("\\A_SIGNED") = true;
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unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
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modified_src_cells = true;
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}
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if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
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if (c1->parameters.at(ID(B_SIGNED)).as_bool() != c2->parameters.at(ID(B_SIGNED)).as_bool())
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{
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RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
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if (unsigned_cell->getPort("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
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RTLIL::SigSpec new_b = unsigned_cell->getPort("\\B");
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RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(B_SIGNED)).as_bool() ? c2 : c1;
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if (unsigned_cell->getPort(ID(B)).to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1;
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RTLIL::SigSpec new_b = unsigned_cell->getPort(ID(B));
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new_b.append_bit(RTLIL::State::S0);
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unsigned_cell->setPort("\\B", new_b);
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unsigned_cell->setPort(ID(B), new_b);
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}
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unsigned_cell->parameters.at("\\B_SIGNED") = true;
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unsigned_cell->parameters.at(ID(B_SIGNED)) = true;
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modified_src_cells = true;
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}
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@ -613,28 +613,28 @@ struct ShareWorker
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c2->check();
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}
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bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
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bool b_signed = c1->parameters.at("\\B_SIGNED").as_bool();
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bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
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bool b_signed = c1->parameters.at(ID(B_SIGNED)).as_bool();
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log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
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log_assert(b_signed == c2->parameters.at("\\B_SIGNED").as_bool());
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log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
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log_assert(b_signed == c2->parameters.at(ID(B_SIGNED)).as_bool());
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if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
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if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
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b_signed = false;
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RTLIL::SigSpec a1 = c1->getPort("\\A");
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RTLIL::SigSpec b1 = c1->getPort("\\B");
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RTLIL::SigSpec y1 = c1->getPort("\\Y");
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RTLIL::SigSpec a1 = c1->getPort(ID(A));
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RTLIL::SigSpec b1 = c1->getPort(ID(B));
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||||
RTLIL::SigSpec y1 = c1->getPort(ID(Y));
|
||||
|
||||
RTLIL::SigSpec a2 = c2->getPort("\\A");
|
||||
RTLIL::SigSpec b2 = c2->getPort("\\B");
|
||||
RTLIL::SigSpec y2 = c2->getPort("\\Y");
|
||||
RTLIL::SigSpec a2 = c2->getPort(ID(A));
|
||||
RTLIL::SigSpec b2 = c2->getPort(ID(B));
|
||||
RTLIL::SigSpec y2 = c2->getPort(ID(Y));
|
||||
|
||||
int a_width = max(a1.size(), a2.size());
|
||||
int b_width = max(b1.size(), b2.size());
|
||||
int y_width = max(y1.size(), y2.size());
|
||||
|
||||
if (c1->type == "$shr" && a_signed)
|
||||
if (c1->type == ID($shr) && a_signed)
|
||||
{
|
||||
a_width = max(y_width, a_width);
|
||||
|
||||
|
|
@ -660,43 +660,43 @@ struct ShareWorker
|
|||
supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b));
|
||||
|
||||
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
|
||||
RTLIL::Wire *x = c1->type == "$alu" ? module->addWire(NEW_ID, y_width) : nullptr;
|
||||
RTLIL::Wire *co = c1->type == "$alu" ? module->addWire(NEW_ID, y_width) : nullptr;
|
||||
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
|
||||
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
|
||||
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
|
||||
supercell->parameters["\\A_SIGNED"] = a_signed;
|
||||
supercell->parameters["\\B_SIGNED"] = b_signed;
|
||||
supercell->parameters["\\A_WIDTH"] = a_width;
|
||||
supercell->parameters["\\B_WIDTH"] = b_width;
|
||||
supercell->parameters["\\Y_WIDTH"] = y_width;
|
||||
supercell->setPort("\\A", a);
|
||||
supercell->setPort("\\B", b);
|
||||
supercell->setPort("\\Y", y);
|
||||
if (c1->type == "$alu") {
|
||||
supercell->parameters[ID(A_SIGNED)] = a_signed;
|
||||
supercell->parameters[ID(B_SIGNED)] = b_signed;
|
||||
supercell->parameters[ID(A_WIDTH)] = a_width;
|
||||
supercell->parameters[ID(B_WIDTH)] = b_width;
|
||||
supercell->parameters[ID(Y_WIDTH)] = y_width;
|
||||
supercell->setPort(ID(A), a);
|
||||
supercell->setPort(ID(B), b);
|
||||
supercell->setPort(ID(Y), y);
|
||||
if (c1->type == ID($alu)) {
|
||||
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
|
||||
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort("\\CI"), c1->getPort("\\CI"), act, ci));
|
||||
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort("\\BI"), c1->getPort("\\BI"), act, bi));
|
||||
supercell->setPort("\\CI", ci);
|
||||
supercell->setPort("\\BI", bi);
|
||||
supercell->setPort("\\CO", co);
|
||||
supercell->setPort("\\X", x);
|
||||
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(CI)), c1->getPort(ID(CI)), act, ci));
|
||||
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(BI)), c1->getPort(ID(BI)), act, bi));
|
||||
supercell->setPort(ID(CI), ci);
|
||||
supercell->setPort(ID(BI), bi);
|
||||
supercell->setPort(ID(CO), co);
|
||||
supercell->setPort(ID(X), x);
|
||||
}
|
||||
supercell->check();
|
||||
|
||||
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
|
||||
if (c1->type == "$alu") {
|
||||
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort("\\CO")));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort("\\CO")));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort("\\X")));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort("\\X")));
|
||||
if (c1->type == ID($alu)) {
|
||||
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID(CO))));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID(CO))));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID(X))));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID(X))));
|
||||
}
|
||||
|
||||
supercell_aux.insert(supercell);
|
||||
return supercell;
|
||||
}
|
||||
|
||||
if (c1->type == "$macc")
|
||||
if (c1->type == ID($macc))
|
||||
{
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
|
||||
supercell_aux.insert(supercell);
|
||||
|
|
@ -705,18 +705,18 @@ struct ShareWorker
|
|||
return supercell;
|
||||
}
|
||||
|
||||
if (c1->type == "$memrd")
|
||||
if (c1->type == ID($memrd))
|
||||
{
|
||||
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
|
||||
RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
|
||||
RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
|
||||
RTLIL::SigSpec addr1 = c1->getPort(ID(ADDR));
|
||||
RTLIL::SigSpec addr2 = c2->getPort(ID(ADDR));
|
||||
if (GetSize(addr1) < GetSize(addr2))
|
||||
addr1.extend_u0(GetSize(addr2));
|
||||
else
|
||||
addr2.extend_u0(GetSize(addr1));
|
||||
supercell->setPort("\\ADDR", addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
|
||||
supercell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr1));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
|
||||
supercell->setPort(ID(ADDR), addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
|
||||
supercell->parameters[ID(ABITS)] = RTLIL::Const(GetSize(addr1));
|
||||
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID(DATA)), c2->getPort(ID(DATA))));
|
||||
supercell_aux.insert(supercell);
|
||||
return supercell;
|
||||
}
|
||||
|
|
@ -747,8 +747,8 @@ struct ShareWorker
|
|||
modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
|
||||
|
||||
for (auto &bit : pbits) {
|
||||
if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S")
|
||||
forbidden_controls_cache[cell].insert(bit.cell->getPort("\\S").extract(bit.offset, 1));
|
||||
if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID(S))
|
||||
forbidden_controls_cache[cell].insert(bit.cell->getPort(ID(S)).extract(bit.offset, 1));
|
||||
consumer_cells.insert(bit.cell);
|
||||
}
|
||||
|
||||
|
|
@ -874,7 +874,7 @@ struct ShareWorker
|
|||
}
|
||||
for (auto &pbit : modwalker.signal_consumers[bit]) {
|
||||
log_assert(fwd_ct.cell_known(pbit.cell->type));
|
||||
if ((pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") && (pbit.port == "\\A" || pbit.port == "\\B"))
|
||||
if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == ID(A) || pbit.port == ID(B)))
|
||||
driven_data_muxes.insert(pbit.cell);
|
||||
else
|
||||
driven_cells.insert(pbit.cell);
|
||||
|
|
@ -890,10 +890,10 @@ struct ShareWorker
|
|||
bool used_in_a = false;
|
||||
std::set<int> used_in_b_parts;
|
||||
|
||||
int width = c->parameters.at("\\WIDTH").as_int();
|
||||
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort("\\A"));
|
||||
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort("\\B"));
|
||||
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort("\\S"));
|
||||
int width = c->parameters.at(ID(WIDTH)).as_int();
|
||||
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID(A)));
|
||||
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID(B)));
|
||||
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID(S)));
|
||||
|
||||
for (auto &bit : sig_a)
|
||||
if (cell_out_bits.count(bit))
|
||||
|
|
@ -1132,14 +1132,14 @@ struct ShareWorker
|
|||
fwd_ct.setup_internals();
|
||||
|
||||
cone_ct.setup_internals();
|
||||
cone_ct.cell_types.erase("$mul");
|
||||
cone_ct.cell_types.erase("$mod");
|
||||
cone_ct.cell_types.erase("$div");
|
||||
cone_ct.cell_types.erase("$pow");
|
||||
cone_ct.cell_types.erase("$shl");
|
||||
cone_ct.cell_types.erase("$shr");
|
||||
cone_ct.cell_types.erase("$sshl");
|
||||
cone_ct.cell_types.erase("$sshr");
|
||||
cone_ct.cell_types.erase(ID($mul));
|
||||
cone_ct.cell_types.erase(ID($mod));
|
||||
cone_ct.cell_types.erase(ID($div));
|
||||
cone_ct.cell_types.erase(ID($pow));
|
||||
cone_ct.cell_types.erase(ID($shl));
|
||||
cone_ct.cell_types.erase(ID($shr));
|
||||
cone_ct.cell_types.erase(ID($sshl));
|
||||
cone_ct.cell_types.erase(ID($sshr));
|
||||
|
||||
modwalker.setup(design, module);
|
||||
|
||||
|
|
@ -1153,9 +1153,9 @@ struct ShareWorker
|
|||
GetSize(shareable_cells), log_id(module));
|
||||
|
||||
for (auto cell : module->cells())
|
||||
if (cell->type == "$pmux")
|
||||
for (auto bit : cell->getPort("\\S"))
|
||||
for (auto other_bit : cell->getPort("\\S"))
|
||||
if (cell->type == ID($pmux))
|
||||
for (auto bit : cell->getPort(ID(S)))
|
||||
for (auto other_bit : cell->getPort(ID(S)))
|
||||
if (bit < other_bit)
|
||||
exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit));
|
||||
|
||||
|
|
@ -1466,43 +1466,43 @@ struct SharePass : public Pass {
|
|||
config.opt_aggressive = false;
|
||||
config.opt_fast = false;
|
||||
|
||||
config.generic_uni_ops.insert("$not");
|
||||
// config.generic_uni_ops.insert("$pos");
|
||||
config.generic_uni_ops.insert("$neg");
|
||||
config.generic_uni_ops.insert(ID($not));
|
||||
// config.generic_uni_ops.insert(ID($pos));
|
||||
config.generic_uni_ops.insert(ID($neg));
|
||||
|
||||
config.generic_cbin_ops.insert("$and");
|
||||
config.generic_cbin_ops.insert("$or");
|
||||
config.generic_cbin_ops.insert("$xor");
|
||||
config.generic_cbin_ops.insert("$xnor");
|
||||
config.generic_cbin_ops.insert(ID($and));
|
||||
config.generic_cbin_ops.insert(ID($or));
|
||||
config.generic_cbin_ops.insert(ID($xor));
|
||||
config.generic_cbin_ops.insert(ID($xnor));
|
||||
|
||||
config.generic_bin_ops.insert("$shl");
|
||||
config.generic_bin_ops.insert("$shr");
|
||||
config.generic_bin_ops.insert("$sshl");
|
||||
config.generic_bin_ops.insert("$sshr");
|
||||
config.generic_bin_ops.insert(ID($shl));
|
||||
config.generic_bin_ops.insert(ID($shr));
|
||||
config.generic_bin_ops.insert(ID($sshl));
|
||||
config.generic_bin_ops.insert(ID($sshr));
|
||||
|
||||
config.generic_bin_ops.insert("$lt");
|
||||
config.generic_bin_ops.insert("$le");
|
||||
config.generic_bin_ops.insert("$eq");
|
||||
config.generic_bin_ops.insert("$ne");
|
||||
config.generic_bin_ops.insert("$eqx");
|
||||
config.generic_bin_ops.insert("$nex");
|
||||
config.generic_bin_ops.insert("$ge");
|
||||
config.generic_bin_ops.insert("$gt");
|
||||
config.generic_bin_ops.insert(ID($lt));
|
||||
config.generic_bin_ops.insert(ID($le));
|
||||
config.generic_bin_ops.insert(ID($eq));
|
||||
config.generic_bin_ops.insert(ID($ne));
|
||||
config.generic_bin_ops.insert(ID($eqx));
|
||||
config.generic_bin_ops.insert(ID($nex));
|
||||
config.generic_bin_ops.insert(ID($ge));
|
||||
config.generic_bin_ops.insert(ID($gt));
|
||||
|
||||
config.generic_cbin_ops.insert("$add");
|
||||
config.generic_cbin_ops.insert("$mul");
|
||||
config.generic_cbin_ops.insert(ID($add));
|
||||
config.generic_cbin_ops.insert(ID($mul));
|
||||
|
||||
config.generic_bin_ops.insert("$sub");
|
||||
config.generic_bin_ops.insert("$div");
|
||||
config.generic_bin_ops.insert("$mod");
|
||||
// config.generic_bin_ops.insert("$pow");
|
||||
config.generic_bin_ops.insert(ID($sub));
|
||||
config.generic_bin_ops.insert(ID($div));
|
||||
config.generic_bin_ops.insert(ID($mod));
|
||||
// config.generic_bin_ops.insert(ID($pow));
|
||||
|
||||
config.generic_uni_ops.insert("$logic_not");
|
||||
config.generic_cbin_ops.insert("$logic_and");
|
||||
config.generic_cbin_ops.insert("$logic_or");
|
||||
config.generic_uni_ops.insert(ID($logic_not));
|
||||
config.generic_cbin_ops.insert(ID($logic_and));
|
||||
config.generic_cbin_ops.insert(ID($logic_or));
|
||||
|
||||
config.generic_other_ops.insert("$alu");
|
||||
config.generic_other_ops.insert("$macc");
|
||||
config.generic_other_ops.insert(ID($alu));
|
||||
config.generic_other_ops.insert(ID($macc));
|
||||
|
||||
log_header(design, "Executing SHARE pass (SAT-based resource sharing).\n");
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue