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Use ID() macro in all of passes/opt/
This was obtained by running the following SED command in passes/opt/ and then using "meld foo.cc foo.cc.orig" to manually fix all resulting compiler errors. sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
b5534b66c8
commit
6995914f3f
12 changed files with 991 additions and 991 deletions
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@ -47,8 +47,8 @@ struct OptMergeWorker
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static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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SigSpec sig_s = conn.at("\\S");
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SigSpec sig_b = conn.at("\\B");
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SigSpec sig_s = conn.at(ID(S));
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SigSpec sig_b = conn.at(ID(B));
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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@ -59,12 +59,12 @@ struct OptMergeWorker
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std::sort(sb_pairs.begin(), sb_pairs.end());
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conn["\\S"] = SigSpec();
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conn["\\B"] = SigSpec();
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conn[ID(S)] = SigSpec();
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conn[ID(B)] = SigSpec();
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for (auto &it : sb_pairs) {
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conn["\\S"].append(it.first);
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conn["\\B"].append(it.second);
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conn[ID(S)].append(it.first);
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conn[ID(B)].append(it.second);
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}
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}
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@ -94,32 +94,32 @@ struct OptMergeWorker
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const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
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if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul",
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"$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) {
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
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ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
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alt_conn = *conn;
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if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
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alt_conn["\\A"] = conn->at("\\B");
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alt_conn["\\B"] = conn->at("\\A");
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if (assign_map(alt_conn.at(ID(A))) < assign_map(alt_conn.at(ID(B)))) {
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alt_conn[ID(A)] = conn->at(ID(B));
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alt_conn[ID(B)] = conn->at(ID(A));
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}
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conn = &alt_conn;
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} else
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if (cell->type.in("$reduce_xor", "$reduce_xnor")) {
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if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at("\\A"));
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alt_conn.at("\\A").sort();
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assign_map.apply(alt_conn.at(ID(A)));
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alt_conn.at(ID(A)).sort();
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conn = &alt_conn;
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} else
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if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) {
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at("\\A"));
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alt_conn.at("\\A").sort_and_unify();
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assign_map.apply(alt_conn.at(ID(A)));
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alt_conn.at(ID(A)).sort_and_unify();
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conn = &alt_conn;
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} else
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if (cell->type == "$pmux") {
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if (cell->type == ID($pmux)) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at("\\A"));
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assign_map.apply(alt_conn.at("\\B"));
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assign_map.apply(alt_conn.at("\\S"));
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assign_map.apply(alt_conn.at(ID(A)));
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assign_map.apply(alt_conn.at(ID(B)));
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assign_map.apply(alt_conn.at(ID(S)));
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sort_pmux_conn(alt_conn);
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conn = &alt_conn;
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}
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@ -189,28 +189,28 @@ struct OptMergeWorker
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assign_map.apply(it.second);
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}
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if (cell1->type == "$and" || cell1->type == "$or" || cell1->type == "$xor" || cell1->type == "$xnor" || cell1->type == "$add" || cell1->type == "$mul" ||
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cell1->type == "$logic_and" || cell1->type == "$logic_or" || cell1->type == "$_AND_" || cell1->type == "$_OR_" || cell1->type == "$_XOR_") {
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if (conn1.at("\\A") < conn1.at("\\B")) {
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RTLIL::SigSpec tmp = conn1["\\A"];
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conn1["\\A"] = conn1["\\B"];
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conn1["\\B"] = tmp;
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if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
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cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) {
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if (conn1.at(ID(A)) < conn1.at(ID(B))) {
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RTLIL::SigSpec tmp = conn1[ID(A)];
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conn1[ID(A)] = conn1[ID(B)];
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conn1[ID(B)] = tmp;
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}
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if (conn2.at("\\A") < conn2.at("\\B")) {
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RTLIL::SigSpec tmp = conn2["\\A"];
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conn2["\\A"] = conn2["\\B"];
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conn2["\\B"] = tmp;
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if (conn2.at(ID(A)) < conn2.at(ID(B))) {
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RTLIL::SigSpec tmp = conn2[ID(A)];
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conn2[ID(A)] = conn2[ID(B)];
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conn2[ID(B)] = tmp;
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}
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} else
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if (cell1->type == "$reduce_xor" || cell1->type == "$reduce_xnor") {
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conn1["\\A"].sort();
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conn2["\\A"].sort();
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if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) {
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conn1[ID(A)].sort();
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conn2[ID(A)].sort();
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} else
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if (cell1->type == "$reduce_and" || cell1->type == "$reduce_or" || cell1->type == "$reduce_bool") {
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conn1["\\A"].sort_and_unify();
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conn2["\\A"].sort_and_unify();
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if (cell1->type == ID($reduce_and) || cell1->type == ID($reduce_or) || cell1->type == ID($reduce_bool)) {
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conn1[ID(A)].sort_and_unify();
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conn2[ID(A)].sort_and_unify();
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} else
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if (cell1->type == "$pmux") {
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if (cell1->type == ID($pmux)) {
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sort_pmux_conn(conn1);
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sort_pmux_conn(conn2);
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}
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@ -222,9 +222,9 @@ struct OptMergeWorker
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return true;
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}
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if (cell1->type.begins_with("$") && conn1.count("\\Q") != 0) {
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std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
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std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
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if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) {
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std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
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std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
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for (size_t i = 0; i < q1.size(); i++)
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if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
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lt = q1.at(i) < q2.at(i);
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@ -271,24 +271,24 @@ struct OptMergeWorker
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ct.setup_stdcells_mem();
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if (mode_nomux) {
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ct.cell_types.erase("$mux");
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ct.cell_types.erase("$pmux");
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ct.cell_types.erase(ID($mux));
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ct.cell_types.erase(ID($pmux));
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}
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ct.cell_types.erase("$tribuf");
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ct.cell_types.erase("$_TBUF_");
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ct.cell_types.erase("$anyseq");
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ct.cell_types.erase("$anyconst");
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ct.cell_types.erase("$allseq");
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ct.cell_types.erase("$allconst");
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ct.cell_types.erase(ID($tribuf));
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ct.cell_types.erase(ID($_TBUF_));
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ct.cell_types.erase(ID($anyseq));
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ct.cell_types.erase(ID($anyconst));
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ct.cell_types.erase(ID($allseq));
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ct.cell_types.erase(ID($allconst));
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log("Finding identical cells in module `%s'.\n", module->name.c_str());
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assign_map.set(module);
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dff_init_map.set(module);
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for (auto &it : module->wires_)
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if (it.second->attributes.count("\\init") != 0) {
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Const initval = it.second->attributes.at("\\init");
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if (it.second->attributes.count(ID(init)) != 0) {
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Const initval = it.second->attributes.at(ID(init));
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for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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dff_init_map.add(SigBit(it.second, i), initval[i]);
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