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Add Xilinx RAM64X1D and RAM128X1D simulation models

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This commit is contained in:
Clifford Wolf 2018-03-07 17:31:07 +01:00
parent 73c01dca65
commit 6991c132b5
4 changed files with 30 additions and 23 deletions
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1
techlibs/xilinx/Makefile.inc
View file

@ -27,7 +27,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v))

30
techlibs/xilinx/cells_sim.v
View file

@ -156,3 +156,33 @@ module FDPE (output reg Q, input C, CE, D, PRE);
endcase endgenerate endcase endgenerate
endmodule endmodule
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [5:0] a = {A5, A4, A3, A2, A1, A0};
wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [63:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
reg [127:0] mem = INIT;
assign SPO = mem[A];
assign DPO = mem[DPRA];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D;
endmodule

20
techlibs/xilinx/drams_bb.v
View file

@ -1,20 +0,0 @@
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -71,7 +71,6 @@ struct SynthXilinxPass : public Pass {
log(" read_verilog -lib +/xilinx/cells_sim.v\n"); log(" read_verilog -lib +/xilinx/cells_sim.v\n");
log(" read_verilog -lib +/xilinx/cells_xtra.v\n"); log(" read_verilog -lib +/xilinx/cells_xtra.v\n");
log(" read_verilog -lib +/xilinx/brams_bb.v\n"); log(" read_verilog -lib +/xilinx/brams_bb.v\n");
log(" read_verilog -lib +/xilinx/drams_bb.v\n");
log(" hierarchy -check -top <top>\n"); log(" hierarchy -check -top <top>\n");
log("\n"); log("\n");
log(" flatten: (only if -flatten)\n"); log(" flatten: (only if -flatten)\n");
@ -168,7 +167,6 @@ struct SynthXilinxPass : public Pass {
Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v");
Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
} }