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Add Xilinx RAM64X1D and RAM128X1D simulation models

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This commit is contained in:
Clifford Wolf 2018-03-07 17:31:07 +01:00
parent 73c01dca65
commit 6991c132b5
4 changed files with 30 additions and 23 deletions
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techlibs/xilinx/Makefile.inc
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@ -27,7 +27,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v))