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https://github.com/YosysHQ/yosys
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patch: fix const handling
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parent
5a6568edbe
commit
698f6e05c0
1 changed files with 12 additions and 12 deletions
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@ -61,11 +61,12 @@ void Patch::collect_src(Cell* old_cell) {
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for (auto [port_name, sig] : old_cell->connections()) {
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auto dir = old_cell->port_dir(port_name);
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log_assert(dir != PD_UNKNOWN);
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log_assert(!sig.size() || sig.is_wire());
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if (dir == PD_INPUT || dir == PD_INOUT) {
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Wire* in_wire = sig.as_wire();
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if (!leaves.count(in_wire))
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inputs.push_back(in_wire->driverCell());
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if (sig.size() && sig.is_wire()) {
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Wire* in_wire = sig.as_wire();
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if (!leaves.count(in_wire))
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inputs.push_back(in_wire->driverCell());
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}
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}
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}
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for (auto input : inputs)
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@ -78,20 +79,19 @@ void Patch::gc(Cell* old_cell) {
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for (auto [port_name, sig] : old_cell->connections()) {
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auto dir = old_cell->port_dir(port_name);
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log_assert(dir != PD_UNKNOWN);
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log_assert(!sig.size() || sig.is_wire());
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if (dir == PD_OUTPUT || dir == PD_INOUT) {
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if (sig.size()) {
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if (sig.size() && sig.is_wire()) {
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if (dir == PD_OUTPUT || dir == PD_INOUT) {
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for (auto bit : sig) {
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// Reject GC if used
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if (!mod->fanout(bit).empty())
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return;
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}
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}
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}
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if (dir == PD_INPUT || dir == PD_INOUT) {
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Wire* in_wire = sig.as_wire();
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if (!leaves.count(in_wire))
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inputs.push_back(in_wire->driverCell());
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if (dir == PD_INPUT || dir == PD_INOUT) {
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Wire* in_wire = sig.as_wire();
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if (!leaves.count(in_wire))
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inputs.push_back(in_wire->driverCell());
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}
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}
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}
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for (auto input : inputs)
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