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Clifford Wolf 2014-02-02 17:57:14 +01:00
parent aa732b0c73
commit 6983d3f10b
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manual/PRESENTATION_ExSyn/proc_02.v Normal file
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module test(input A, B, C, D, E,
output reg Y);
always @* begin
Y <= A;
if (B)
Y <= C;
if (D)
Y <= E;
end
endmodule