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presentation progress

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Clifford Wolf 2014-02-02 17:57:14 +01:00
parent aa732b0c73
commit 6983d3f10b
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7
manual/PRESENTATION_ExSyn/proc_00.v Normal file
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module test(input D, C, R, output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
endmodule