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presentation progress

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Clifford Wolf 2014-02-02 17:57:14 +01:00
parent aa732b0c73
commit 6983d3f10b
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manual/PRESENTATION_ExSyn/.gitignore vendored Normal file
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*.dot

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manual/PRESENTATION_ExSyn/Makefile Normal file
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all: proc_00.pdf proc_01.pdf proc_02.pdf
proc_00.pdf: proc_00.v proc_00.ys
../../yosys -p 'script proc_00.ys; show -notitle -prefix proc_00 -format pdf'
proc_01.pdf: proc_01.v proc_01.ys
../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf'
proc_02.pdf: proc_02.v proc_02.ys
../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf'

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manual/PRESENTATION_ExSyn/proc_00.v Normal file
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module test(input D, C, R, output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
endmodule

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manual/PRESENTATION_ExSyn/proc_00.ys Normal file
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read_verilog proc_00.v
hierarchy -check -top test
proc;;

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manual/PRESENTATION_ExSyn/proc_01.v Normal file
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module test(input D, C, R, RV,
output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= RV;
else
Q <= D;
endmodule

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manual/PRESENTATION_ExSyn/proc_01.ys Normal file
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read_verilog proc_01.v
hierarchy -check -top test
proc;;

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manual/PRESENTATION_ExSyn/proc_02.v Normal file
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module test(input A, B, C, D, E,
output reg Y);
always @* begin
Y <= A;
if (B)
Y <= C;
if (D)
Y <= E;
end
endmodule

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manual/PRESENTATION_ExSyn/proc_02.ys Normal file
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read_verilog proc_02.v
hierarchy -check -top test
proc;;