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Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API

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This commit is contained in:
Clifford Wolf 2013-06-18 17:11:13 +02:00
parent 5cf04f33fa
commit 6971c4db62
2 changed files with 79 additions and 2 deletions
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33
kernel/rtlil.cc
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@ -340,18 +340,47 @@ void RTLIL::Module::optimize()
}
}
void RTLIL::Module::add(RTLIL::Wire *wire) {
void RTLIL::Module::add(RTLIL::Wire *wire)
{
assert(!wire->name.empty());
assert(count_id(wire->name) == 0);
wires[wire->name] = wire;
}
void RTLIL::Module::add(RTLIL::Cell *cell) {
void RTLIL::Module::add(RTLIL::Cell *cell)
{
assert(!cell->name.empty());
assert(count_id(cell->name) == 0);
cells[cell->name] = cell;
}
static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->port_id && !b->port_id)
return true;
if (!a->port_id && b->port_id)
return false;
if (a->port_id == b->port_id)
return a->name < b->name;
return a->port_id < b->port_id;
}
void RTLIL::Module::fixup_ports()
{
std::vector<RTLIL::Wire*> all_ports;
for (auto &w : wires)
if (w.second->port_input || w.second->port_output)
all_ports.push_back(w.second);
else
w.second->port_id = 0;
std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
for (size_t i = 0; i < all_ports.size(); i++)
all_ports[i]->port_id = i+1;
}
RTLIL::Wire::Wire()
{
width = 1;