mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 13:18:56 +00:00
fix a few bugs in the functional backend and refactor the testing
This commit is contained in:
Emily Schmidt
parent
674e6d201d
commit
6922633b0b
6 changed files with 366 additions and 270 deletions
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@ -1,30 +1,6 @@
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from itertools import chain
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import random
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widths = [
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(16, 32, 48, True),
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(16, 32, 48, False),
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(32, 16, 48, True),
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(32, 16, 48, False),
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(32, 32, 16, True),
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(32, 32, 16, False)
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]
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shift_widths = [
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(32, 6, 32, True, False),
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(32, 6, 32, False, False),
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(32, 6, 64, True, False),
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(32, 6, 64, False, False),
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(32, 32, 16, True, False),
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(32, 32, 16, False, False),
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(32, 6, 32, True, True),
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(32, 6, 32, False, True),
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(32, 6, 64, True, True),
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(32, 6, 64, False, True),
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(32, 32, 16, True, True),
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(32, 32, 16, False, True),
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]
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def write_rtlil_cell(f, cell_type, inputs, outputs, parameters):
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f.write('autoidx 1\n')
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f.write('module \\gold\n')
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@ -37,207 +13,260 @@ def write_rtlil_cell(f, cell_type, inputs, outputs, parameters):
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idx += 1
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f.write(f'\tcell ${cell_type} \\UUT\n')
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for (name, value) in parameters.items():
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f.write(f'\t\tparameter \\{name} {value}\n')
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if value >= 2**32:
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f.write(f'\t\tparameter \\{name} {value.bit_length()}\'{value:b}\n')
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else:
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f.write(f'\t\tparameter \\{name} {value}\n')
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for name in chain(inputs.keys(), outputs.keys()):
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f.write(f'\t\tconnect \\{name} \\{name}\n')
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f.write(f'\tend\nend\n')
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class BaseCell:
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def __init__(self, name):
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def __init__(self, name, parameters, inputs, outputs, test_values):
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self.name = name
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self.parameters = parameters
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self.inputs = inputs
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self.outputs = outputs
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self.test_values = test_values
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def get_port_width(self, port, parameters):
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def parse_specifier(spec):
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if isinstance(spec, int):
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return spec
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if isinstance(spec, str):
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return parameters[spec]
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if callable(spec):
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return spec(parameters)
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assert False, "expected int, str or lambda"
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if port in self.inputs:
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return parse_specifier(self.inputs[port])
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elif port in self.outputs:
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return parse_specifier(self.outputs[port])
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else:
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assert False, "expected input or output"
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def generate_tests(self, rnd):
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def print_parameter(v):
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if isinstance(v, bool):
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return "S" if v else "U"
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else:
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return str(v)
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for values in self.test_values:
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if isinstance(values, int):
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values = [values]
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name = '-'.join([print_parameter(v) for v in values])
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parameters = {parameter: int(values[i]) for i, parameter in enumerate(self.parameters)}
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if self.is_test_valid(values):
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yield (name, parameters)
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def write_rtlil_file(self, path, parameters):
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inputs = {port: self.get_port_width(port, parameters) for port in self.inputs}
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outputs = {port: self.get_port_width(port, parameters) for port in self.outputs}
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with open(path, 'w') as f:
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write_rtlil_cell(f, self.name, inputs, outputs, parameters)
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def is_test_valid(self, values):
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return True
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class UnaryCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, _, y_width, signed) in widths:
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yield (f'{a_width}-{y_width}-{'S' if signed else 'U'}',
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{'A_WIDTH' : a_width,
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'A_SIGNED' : int(signed),
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'Y_WIDTH' : y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'Y_WIDTH', 'A_SIGNED'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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class BinaryCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, b_width, y_width, signed) in widths:
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yield (f'{a_width}-{b_width}-{y_width}-{'S' if signed else 'U'}',
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{'A_WIDTH' : a_width,
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'A_SIGNED' : int(signed),
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'B_WIDTH' : b_width,
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'B_SIGNED' : int(signed),
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'Y_WIDTH' : y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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class ShiftCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, b_width, y_width, a_signed, b_signed) in shift_widths:
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if not self.name in ('shift', 'shiftx') and b_signed: continue
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if self.name == 'shiftx' and a_signed: continue
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yield (f'{a_width}-{b_width}-{y_width}-{'S' if a_signed else 'U'}{'S' if b_signed else 'U'}',
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{'A_WIDTH' : a_width,
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'A_SIGNED' : int(a_signed),
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'B_WIDTH' : b_width,
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'B_SIGNED' : int(b_signed),
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'Y_WIDTH' : y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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def is_test_valid(self, values):
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(a_width, b_width, y_width, a_signed, b_signed) = values
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if not self.name in ('shift', 'shiftx') and b_signed: return False
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if self.name == 'shiftx' and a_signed: return False
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return True
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class MuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for width in [10, 20, 40]:
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yield (f'{width}', {'WIDTH' : width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': parameters['WIDTH'], 'S': 1}, {'Y': parameters['WIDTH']}, parameters)
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'S': 1}, {'Y': 'WIDTH'}, values)
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class BWCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for width in [10, 20, 40]:
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yield (f'{width}', {'WIDTH' : width})
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def write_rtlil_file(self, f, parameters):
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inputs = {'A': parameters['WIDTH'], 'B': parameters['WIDTH']}
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if self.name == "bwmux": inputs['S'] = parameters['WIDTH']
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write_rtlil_cell(f, self.name, inputs, {'Y': parameters['WIDTH']}, parameters)
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def __init__(self, name, values):
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inputs = {'A': 'WIDTH', 'B': 'WIDTH'}
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if name == "bwmux": inputs['S'] = 'WIDTH'
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super().__init__(name, ['WIDTH'], inputs, {'Y': 'WIDTH'}, values)
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class PMuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (width, s_width) in [(10, 1), (10, 4), (20, 4)]:
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yield (f'{width}-{s_width}',
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{'WIDTH' : width,
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'S_WIDTH' : s_width})
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def write_rtlil_file(self, f, parameters):
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s_width = parameters['S_WIDTH']
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b_width = parameters['WIDTH'] * s_width
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': b_width, 'S': s_width}, {'Y': parameters['WIDTH']}, parameters)
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def __init__(self, name, values):
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b_width = lambda par: par['WIDTH'] * par['S_WIDTH']
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super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'B': b_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values)
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class BMuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (width, s_width) in [(10, 1), (10, 2), (10, 4)]:
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yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'] << parameters['S_WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH']}, parameters)
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def __init__(self, name, values):
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a_width = lambda par: par['WIDTH'] << par['S_WIDTH']
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super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': a_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values)
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class DemuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (width, s_width) in [(10, 1), (32, 2), (16, 4)]:
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yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH'] << parameters['S_WIDTH']}, parameters)
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def seeded_randint(seed, a, b):
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r = random.getstate()
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random.seed(seed)
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n = random.randint(a, b)
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random.setstate(r)
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return n
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def __init__(self, name, values):
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y_width = lambda par: par['WIDTH'] << par['S_WIDTH']
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super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'S': 'S_WIDTH'}, {'Y': y_width}, values)
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class LUTCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for width in [4, 6, 8]:
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lut = seeded_randint(width, 0, 2**width - 1)
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH', 'LUT'], {'A': 'WIDTH'}, {'Y': 1}, values)
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def generate_tests(self, rnd):
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for width in self.test_values:
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lut = rnd(f'lut-{width}').getrandbits(2**width)
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yield (f'{width}', {'WIDTH' : width, 'LUT' : lut})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH']}, {'Y': 1}, parameters)
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class ConcatCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, b_width) in [(16, 16), (8, 14), (20, 10)]:
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yield (f'{a_width}-{b_width}', {'A_WIDTH' : a_width, 'B_WIDTH' : b_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B' : parameters['B_WIDTH']}, {'Y': parameters['A_WIDTH'] + parameters['B_WIDTH']}, parameters)
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def __init__(self, name, values):
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y_width = lambda par: par['A_WIDTH'] + par['B_WIDTH']
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super().__init__(name, ['A_WIDTH', 'B_WIDTH'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': y_width}, values)
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class SliceCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, offset, y_width) in [(32, 10, 15), (8, 0, 4), (10, 0, 10)]:
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yield (f'{a_width}-{offset}-{y_width}', {'A_WIDTH' : a_width, 'OFFSET' : offset, 'Y_WIDTH': y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'OFFSET', 'Y_WIDTH'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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class FailCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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super().__init__(name, [], {}, {})
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def generate_tests(self, rnd):
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yield ('', {})
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def write_rtlil_file(self, f, parameters):
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def write_rtlil_file(self, path, parameters):
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raise Exception(f'\'{self.name}\' cell unimplemented in test generator')
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class FFCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], ['D'], ['Q'], values)
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def write_rtlil_file(self, path, parameters):
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from test_functional import yosys_synth
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verilog_file = path.parent / 'verilog.v'
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with open(verilog_file, 'w') as f:
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f.write("""
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module gold(
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input wire clk,
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input wire [{0}:0] D,
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output reg [{0}:0] Q
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);
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always @(posedge clk)
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Q <= D;
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endmodule""".format(parameters['WIDTH'] - 1))
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yosys_synth(verilog_file, path)
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class MemCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'], {'WA': 'ADDR_WIDTH', 'RA': 'ADDR_WIDTH', 'WD': 'DATA_WIDTH'}, {'RD': 'DATA_WIDTH'}, values)
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def write_rtlil_file(self, path, parameters):
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from test_functional import yosys_synth
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verilog_file = path.parent / 'verilog.v'
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with open(verilog_file, 'w') as f:
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f.write("""
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module gold(
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input wire clk,
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input wire [{1}:0] WA,
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input wire [{0}:0] WD,
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output reg [{0}:0] RD
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);
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reg [{0}:0] mem[0:{1}];
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always @(*)
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RD = mem[RA];
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always @(posedge clk)
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mem[WA] <= WD;
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endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1))
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yosys_synth(verilog_file, path)
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binary_widths = [
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# try to cover extending A operand, extending B operand, extending/truncating result
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(16, 32, 48, True, True),
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(16, 32, 48, False, False),
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(32, 16, 48, True, True),
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(32, 16, 48, False, False),
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(32, 32, 16, True, True),
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(32, 32, 16, False, False),
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# have at least one test that checks small inputs, which will exercise the cornercases more
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(4, 4, 8, True, True),
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(4, 4, 8, False, False)
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]
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unary_widths = [
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(6, 12, True),
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(6, 12, False),
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(32, 16, True),
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(32, 16, False)
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]
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# note that meaningless combinations of signednesses are eliminated,
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# like e.g. most shift operations don't take signed shift amounts
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shift_widths = [
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# one set of tests that definitely checks all possible shift amounts
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# with a bigger result width to make sure it's not truncated
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(32, 6, 64, True, False),
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(32, 6, 64, False, False),
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(32, 6, 64, True, True),
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(32, 6, 64, False, True),
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# one set that checks very oversized shifts
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(32, 32, 64, True, False),
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(32, 32, 64, False, False),
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(32, 32, 64, True, True),
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(32, 32, 64, False, True),
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# at least one test where the result is going to be truncated
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(32, 6, 16, False, False)
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]
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rtlil_cells = [
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UnaryCell("not"),
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UnaryCell("pos"),
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UnaryCell("neg"),
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BinaryCell("and"),
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BinaryCell("or"),
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BinaryCell("xor"),
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BinaryCell("xnor"),
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UnaryCell("reduce_and"),
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UnaryCell("reduce_or"),
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UnaryCell("reduce_xor"),
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UnaryCell("reduce_xnor"),
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UnaryCell("reduce_bool"),
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ShiftCell("shl"),
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ShiftCell("shr"),
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ShiftCell("sshl"),
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ShiftCell("sshr"),
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ShiftCell("shift"),
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ShiftCell("shiftx"),
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UnaryCell("not", unary_widths),
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UnaryCell("pos", unary_widths),
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UnaryCell("neg", unary_widths),
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BinaryCell("and", binary_widths),
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BinaryCell("or", binary_widths),
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BinaryCell("xor", binary_widths),
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BinaryCell("xnor", binary_widths),
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UnaryCell("reduce_and", unary_widths),
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UnaryCell("reduce_or", unary_widths),
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UnaryCell("reduce_xor", unary_widths),
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UnaryCell("reduce_xnor", unary_widths),
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UnaryCell("reduce_bool", unary_widths),
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ShiftCell("shl", shift_widths),
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ShiftCell("shr", shift_widths),
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ShiftCell("sshl", shift_widths),
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ShiftCell("sshr", shift_widths),
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ShiftCell("shift", shift_widths),
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ShiftCell("shiftx", shift_widths),
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# ("fa", ["A", "B", "C", "X", "Y"]),
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# ("lcu", ["P", "G", "CI", "CO"]),
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# ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]),
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BinaryCell("lt"),
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BinaryCell("le"),
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BinaryCell("eq"),
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BinaryCell("ne"),
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BinaryCell("eqx"),
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||||
BinaryCell("nex"),
|
||||
BinaryCell("ge"),
|
||||
BinaryCell("gt"),
|
||||
BinaryCell("add"),
|
||||
BinaryCell("sub"),
|
||||
BinaryCell("mul"),
|
||||
BinaryCell("lt", binary_widths),
|
||||
BinaryCell("le", binary_widths),
|
||||
BinaryCell("eq", binary_widths),
|
||||
BinaryCell("ne", binary_widths),
|
||||
BinaryCell("eqx", binary_widths),
|
||||
BinaryCell("nex", binary_widths),
|
||||
BinaryCell("ge", binary_widths),
|
||||
BinaryCell("gt", binary_widths),
|
||||
BinaryCell("add", binary_widths),
|
||||
BinaryCell("sub", binary_widths),
|
||||
BinaryCell("mul", binary_widths),
|
||||
# BinaryCell("macc"),
|
||||
BinaryCell("div"),
|
||||
BinaryCell("mod"),
|
||||
BinaryCell("divfloor"),
|
||||
BinaryCell("modfloor"),
|
||||
BinaryCell("pow"),
|
||||
UnaryCell("logic_not"),
|
||||
BinaryCell("logic_and"),
|
||||
BinaryCell("logic_or"),
|
||||
SliceCell("slice"),
|
||||
ConcatCell("concat"),
|
||||
MuxCell("mux"),
|
||||
BMuxCell("bmux"),
|
||||
PMuxCell("pmux"),
|
||||
DemuxCell("demux"),
|
||||
LUTCell("lut"),
|
||||
BinaryCell("div", binary_widths),
|
||||
BinaryCell("mod", binary_widths),
|
||||
BinaryCell("divfloor", binary_widths),
|
||||
BinaryCell("modfloor", binary_widths),
|
||||
BinaryCell("pow", binary_widths),
|
||||
UnaryCell("logic_not", unary_widths),
|
||||
BinaryCell("logic_and", binary_widths),
|
||||
BinaryCell("logic_or", binary_widths),
|
||||
SliceCell("slice", [(32, 10, 15), (8, 0, 4), (10, 0, 10)]),
|
||||
ConcatCell("concat", [(16, 16), (8, 14), (20, 10)]),
|
||||
MuxCell("mux", [10, 16, 40]),
|
||||
BMuxCell("bmux", [(10, 1), (10, 2), (10, 4)]),
|
||||
PMuxCell("pmux", [(10, 1), (10, 4), (20, 4)]),
|
||||
DemuxCell("demux", [(10, 1), (32, 2), (16, 4)]),
|
||||
LUTCell("lut", [4, 6, 8]),
|
||||
# ("sop", ["A", "Y"]),
|
||||
# ("tribuf", ["A", "EN", "Y"]),
|
||||
# ("specify2", ["EN", "SRC", "DST"]),
|
||||
# ("specify3", ["EN", "SRC", "DST", "DAT"]),
|
||||
# ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]),
|
||||
BWCell("bweqx"),
|
||||
BWCell("bwmux"),
|
||||
BWCell("bweqx", [10, 16, 40]),
|
||||
BWCell("bwmux", [10, 16, 40]),
|
||||
FFCell("ff", [10, 20, 40]),
|
||||
MemCell("mem", [(32, 4)])
|
||||
# ("assert", ["A", "EN"]),
|
||||
# ("assume", ["A", "EN"]),
|
||||
# ("live", ["A", "EN"]),
|
||||
|
|
@ -260,12 +289,12 @@ rtlil_cells = [
|
|||
# ("scopeinfo", []),
|
||||
]
|
||||
|
||||
def generate_test_cases(per_cell):
|
||||
def generate_test_cases(per_cell, rnd):
|
||||
tests = []
|
||||
names = []
|
||||
for cell in rtlil_cells:
|
||||
seen_names = set()
|
||||
for (name, parameters) in cell.generate_tests():
|
||||
for (name, parameters) in cell.generate_tests(rnd):
|
||||
if not name in seen_names:
|
||||
seen_names.add(name)
|
||||
tests.append((cell, parameters))
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue