mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-29 07:27:58 +00:00
Code Activity

Merge branch 'master' into xc7dsp

Browse source
This commit is contained in:
David Shah 2019-08-30 13:57:15 +01:00
commit 6919c0f9b0
190 changed files with 8815 additions and 4357 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/common/synth.cc
View file

@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass
log_cmd_error("This command only operates on fully selected designs!\n");
if (abc == "abc9" && !lut)
log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)");
log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
log_header(design, "Executing SYNTH pass.\n");
log_push();