mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 03:45:52 +00:00
Code Activity

hashlib: redo interface for flexibility

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-10-01 15:12:03 +02:00
parent 0ab9fccbf1
commit 68e40d8563
36 changed files with 461 additions and 357 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/proc/proc_mux.cc
View file

@ -108,8 +108,8 @@ struct SigSnippets
struct SnippetSwCache
{
dict<RTLIL::SwitchRule*, pool<RTLIL::SigBit>, hash_ptr_ops> full_case_bits_cache;
dict<RTLIL::SwitchRule*, pool<int>, hash_ptr_ops> cache;
dict<RTLIL::SwitchRule*, pool<RTLIL::SigBit>> full_case_bits_cache;
dict<RTLIL::SwitchRule*, pool<int>> cache;
const SigSnippets *snippets;
int current_snippet;
@ -318,7 +318,7 @@ const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRul
return swcache.full_case_bits_cache.at(sw);
}
RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, dict<RTLIL::SwitchRule*, bool, hash_ptr_ops> &swpara,
RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, dict<RTLIL::SwitchRule*, bool> &swpara,
RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval, bool ifxmode)
{
RTLIL::SigSpec result = defval;
@ -421,7 +421,7 @@ void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode)
swcache.snippets = &sigsnip;
swcache.insert(&proc->root_case);
dict<RTLIL::SwitchRule*, bool, hash_ptr_ops> swpara;
dict<RTLIL::SwitchRule*, bool> swpara;
int cnt = 0;
for (int idx : sigsnip.snippets)