mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Clean up pseudo-private member usage in backends/spice/spice.cc.

Browse source
This commit is contained in:
Alberto Gonzalez 2020-04-01 04:56:52 +00:00
parent 057976c323
commit 68c0e3562e
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 9 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
backends/spice/spice.cc
View file

@ -70,14 +70,13 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
idict<IdString, 1> inums; idict<IdString, 1> inums;
int cell_counter = 0, conn_counter = 0, nc_counter = 0; int cell_counter = 0, conn_counter = 0, nc_counter = 0;
for (auto &cell_it : module->cells_) for (auto cell : module->cells())
{ {
RTLIL::Cell *cell = cell_it.second;
f << stringf("X%d", cell_counter++); f << stringf("X%d", cell_counter++);
std::vector<RTLIL::SigSpec> port_sigs; std::vector<RTLIL::SigSpec> port_sigs;
if (design->modules_.count(cell->type) == 0) if (design->module(cell->type) == nullptr)
{ {
log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n", log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
log_id(cell->type), log_id(module), log_id(cell)); log_id(cell->type), log_id(module), log_id(cell));
@ -88,11 +87,10 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
} }
else else
{ {
RTLIL::Module *mod = design->modules_.at(cell->type); RTLIL::Module *mod = design->module(cell->type);
std::vector<RTLIL::Wire*> ports; std::vector<RTLIL::Wire*> ports;
for (auto wire_it : mod->wires_) { for (auto wire : mod->wires()) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0) if (wire->port_id == 0)
continue; continue;
while (int(ports.size()) < wire->port_id) while (int(ports.size()) < wire->port_id)
@ -202,16 +200,15 @@ struct SpiceBackend : public Backend {
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
if (top_module_name.empty()) if (top_module_name.empty())
for (auto & mod_it:design->modules_) for (auto module : design->modules())
if (mod_it.second->get_bool_attribute("\\top")) if (module->get_bool_attribute("\\top"))
top_module_name = mod_it.first.str(); top_module_name = module->name.str();
*f << stringf("* SPICE netlist generated by %s\n", yosys_version_str); *f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
*f << stringf("\n"); *f << stringf("\n");
for (auto module_it : design->modules_) for (auto module : design->modules())
{ {
RTLIL::Module *module = module_it.second;
if (module->get_blackbox_attribute()) if (module->get_blackbox_attribute())
continue; continue;
@ -226,8 +223,7 @@ struct SpiceBackend : public Backend {
} }
std::vector<RTLIL::Wire*> ports; std::vector<RTLIL::Wire*> ports;
for (auto wire_it : module->wires_) { for (auto wire : module->wires()) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0) if (wire->port_id == 0)
continue; continue;
while (int(ports.size()) < wire->port_id) while (int(ports.size()) < wire->port_id)