From 6882eb670a97cbf1114600a92a710e50ea4627ed Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Sat, 7 Feb 2026 00:52:29 +0100 Subject: [PATCH] tests: fix fsm.ys --- tests/arch/ecp5/fsm.ys | 2 +- tests/arch/quicklogic/qlf_k6n10f/fsm.ys | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/arch/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys index 45b96ac63..06495624b 100644 --- a/tests/arch/ecp5/fsm.ys +++ b/tests/arch/ecp5/fsm.ys @@ -5,7 +5,7 @@ flatten equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 miter -equiv -make_assert -flatten gold gate miter -techmap -map +/dff2ff.v +formalff -clk2ff sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/quicklogic/qlf_k6n10f/fsm.ys b/tests/arch/quicklogic/qlf_k6n10f/fsm.ys index e7a9d962d..8b4387f0e 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/fsm.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/fsm.ys @@ -5,6 +5,7 @@ flatten equiv_opt -run :prove -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f async2sync +formalff -clk2ff miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter