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clockgate: formal liberty tests

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This commit is contained in:
Emil J. Tywoniak 2026-05-07 16:08:55 +02:00
parent f4a10a4808
commit 687e5442f2
5 changed files with 107 additions and 100 deletions
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8
tests/techmap/clockgate_wide.v Normal file
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module dffe_wide_11( input clk, input [1:0] en,
input [3:0] d1, output reg [3:0] q1,
);
always @( posedge clk ) begin
if ( en[0] )
q1 <= d1;
end
endmodule