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clockgate: formal liberty tests
This commit is contained in:
Emil J. Tywoniak
parent
f4a10a4808
commit
687e5442f2
5 changed files with 107 additions and 100 deletions
208
tests/techmap/clockgate.tcl
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208
tests/techmap/clockgate.tcl
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yosys -import
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read_verilog clockgate.v
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yosys proc
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opt
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design -save before
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#------------------------------------------------------------------------------
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# Test -pos
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops don't get matched on -pos
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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# rising edge clock flops do get matched on -pos
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select -module dffe_10 -assert-count 1 t:\\pdk_icg
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select -module dffe_11 -assert-count 1 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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# Extra credit: multi-bit FFs work fine as well
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select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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# Test -neg
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design -load before
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clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops do get matched on -neg
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select -module dffe_00 -assert-count 1 t:\\pdk_icg
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select -module dffe_01 -assert-count 1 t:\\pdk_icg
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# rising edge clock flops don't get matched on -neg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_00 -assert-count 1 t:\$_NOT_
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select -module dffe_01 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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# Same as first case, but on fine-grained cells
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design -load before
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techmap
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops don't get matched on -pos
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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# falling edge clock flops do get matched on -pos
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select -module dffe_10 -assert-count 1 t:\\pdk_icg
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select -module dffe_11 -assert-count 1 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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# Extra credit: multi-bit FFs work fine as well
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select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -load before
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clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# No FF set sharing a (clock, clock enable) pair is large enough
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -reset
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read_rtlil clockgate_bad.il
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# Check we don't choke on constants
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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select -module bad1 -assert-count 0 t:\\pdk_icg
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select -module bad2 -assert-count 0 t:\\pdk_icg
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#------------------------------------------------------------------------------
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# Regression test: EN is a bit from a multi-bit wire
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design -reset
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read_verilog clockgate_wide.v
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yosys proc
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opt
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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select -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -reset
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read_liberty c*ckgate.lib
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design -save map
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foreach mod {dffe_00 dffe_01 dffe_10 dffe_11} {
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design -load before
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hierarchy -top $mod
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read_liberty -lib c*ckgate.lib
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equiv_opt -map %map -multiclock clockgate -liberty c*ckgate.lib
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design -load postopt
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design -copy-to final $mod
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}
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design -load final
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# rising edge ICGs
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select -module dffe_00 -assert-count 0 t:\\pos_small
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select -module dffe_01 -assert-count 0 t:\\pos_small
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select -module dffe_10 -assert-count 1 t:\\pos_small
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select -module dffe_11 -assert-count 1 t:\\pos_small
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# falling edge ICGs
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select -module dffe_00 -assert-count 1 t:\\neg_small
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select -module dffe_01 -assert-count 1 t:\\neg_small
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select -module dffe_10 -assert-count 0 t:\\neg_small
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select -module dffe_11 -assert-count 0 t:\\neg_small
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# and nothing else
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select -module dffe_00 -assert-count 0 t:\\pos_big
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select -module dffe_01 -assert-count 0 t:\\pos_big
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select -module dffe_10 -assert-count 0 t:\\pos_big
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select -module dffe_11 -assert-count 0 t:\\pos_big
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select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_00 -assert-count 0 t:\\neg_big
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select -module dffe_01 -assert-count 0 t:\\neg_big
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select -module dffe_10 -assert-count 0 t:\\neg_big
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select -module dffe_11 -assert-count 0 t:\\neg_big
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select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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# test multiple liberty files to behave the same way
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design -load before
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clockgate -liberty clockgate_pos.lib -liberty clockgate_neg.lib
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# rising edge ICGs
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select -module dffe_00 -assert-count 0 t:\\pos_small
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select -module dffe_01 -assert-count 0 t:\\pos_small
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select -module dffe_10 -assert-count 1 t:\\pos_small
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select -module dffe_11 -assert-count 1 t:\\pos_small
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# falling edge ICGs
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select -module dffe_00 -assert-count 1 t:\\neg_small
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select -module dffe_01 -assert-count 1 t:\\neg_small
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select -module dffe_10 -assert-count 0 t:\\neg_small
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select -module dffe_11 -assert-count 0 t:\\neg_small
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# and nothing else
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select -module dffe_00 -assert-count 0 t:\\pos_big
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select -module dffe_01 -assert-count 0 t:\\pos_big
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select -module dffe_10 -assert-count 0 t:\\pos_big
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select -module dffe_11 -assert-count 0 t:\\pos_big
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select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
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select -module dffe_00 -assert-count 0 t:\\neg_big
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select -module dffe_01 -assert-count 0 t:\\neg_big
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select -module dffe_10 -assert-count 0 t:\\neg_big
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select -module dffe_11 -assert-count 0 t:\\neg_big
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select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
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select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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design -load before
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clockgate -liberty clockgate.lib -dont_use pos_small -dont_use neg_small
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# rising edge ICGs
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select -module dffe_10 -assert-count 1 t:\\pos_big
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select -module dffe_11 -assert-count 1 t:\\pos_big
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# falling edge ICGs
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select -module dffe_00 -assert-count 1 t:\\neg_big
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select -module dffe_01 -assert-count 1 t:\\neg_big
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