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Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap

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This commit is contained in:
Eddie Hung 2019-08-23 10:00:50 -07:00
commit 6872805a3e
146 changed files with 4377 additions and 1490 deletions
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4
techlibs/xilinx/Makefile.inc
View file

@ -32,8 +32,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))

34
techlibs/xilinx/cells_sim.v
View file

@ -196,8 +196,14 @@ module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry *) output [3:0] CO,
output [3:0] O,
(* abc_carry *) input CI,
input CYINIT,
input [3:0] DI, S
);
assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
@ -304,12 +310,12 @@ module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* abc_box_id = 5, abc_scc_break="D,WE" *)
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
(* clkbuf_sink *)
input WCLK,
input D, WE,
(* abc_scc_break *) input D,
(* clkbuf_sink *) input WCLK,
(* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@ -324,12 +330,12 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 6, abc_scc_break="D,WE" *)
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
(* clkbuf_sink *)
input WCLK,
input D, WE,
(* abc_scc_break *) input D,
(* clkbuf_sink *) input WCLK,
(* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@ -344,12 +350,12 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 7, abc_scc_break="D,WE" *)
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
input D, WE,
(* clkbuf_sink *)
input WCLK,
(* abc_scc_break *) input D,
(* clkbuf_sink *) input WCLK,
(* abc_scc_break *) input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;

0
techlibs/xilinx/drams.txt → techlibs/xilinx/lutrams.txt
View file

0
techlibs/xilinx/drams_map.v → techlibs/xilinx/lutrams_map.v
View file

31
techlibs/xilinx/synth_xilinx.cc
View file

@ -67,13 +67,13 @@ struct SynthXilinxPass : public ScriptPass
log(" generate an output netlist suitable for ISE (enables -iopad)\n");
log("\n");
log(" -nobram\n");
log(" disable inference of block rams\n");
log(" do not use block RAM cells in output netlist\n");
log("\n");
log(" -nodram\n");
log(" disable inference of distributed rams\n");
log(" -nolutram\n");
log(" do not use distributed RAM cells in output netlist\n");
log("\n");
log(" -nosrl\n");
log(" disable inference of shift registers\n");
log(" do not use distributed SRL cells in output netlist\n");
log("\n");
log(" -nocarry\n");
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
@ -116,7 +116,7 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
int widemux;
void clear_flags() YS_OVERRIDE
@ -134,7 +134,7 @@ struct SynthXilinxPass : public ScriptPass
noclkbuf = false;
nocarry = false;
nobram = false;
nodram = false;
nolutram = false;
nosrl = false;
nocarry = false;
nowidelut = false;
@ -218,8 +218,8 @@ struct SynthXilinxPass : public ScriptPass
nobram = true;
continue;
}
if (args[argidx] == "-nodram") {
nodram = true;
if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
nolutram = true;
continue;
}
if (args[argidx] == "-nosrl") {
@ -316,7 +316,7 @@ struct SynthXilinxPass : public ScriptPass
run("opt_clean");
}
if (check_label("bram", "(skip if '-nobram')")) {
if (check_label("map_bram", "(skip if '-nobram')")) {
if (help_mode) {
run("memory_bram -rules +/xilinx/{family}_brams.txt");
run("techmap -map +/xilinx/{family}_brams_map.v");
@ -333,20 +333,23 @@ struct SynthXilinxPass : public ScriptPass
}
}
if (check_label("dram", "(skip if '-nodram')")) {
if (!nodram || help_mode) {
run("memory_bram -rules +/xilinx/drams.txt");
run("techmap -map +/xilinx/drams_map.v");
if (check_label("map_lutram", "(skip if '-nolutram')")) {
if (!nolutram || help_mode) {
run("memory_bram -rules +/xilinx/lutrams.txt");
run("techmap -map +/xilinx/lutrams_map.v");
}
}
if (check_label("fine")) {
if (check_label("map_ffram")) {
if (widemux > 0)
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
// performs less efficiently
else
run("opt -fast -full");
run("memory_map");
}
if (check_label("fine")) {
run("dffsr2dff");
run("dff2dffe");
if (help_mode) {