mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-02 04:27:53 +00:00
Code Activity

Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap

Browse source
This commit is contained in:
Eddie Hung 2019-08-23 10:00:50 -07:00
commit 6872805a3e
146 changed files with 4377 additions and 1490 deletions
Download patch file Download diff file Expand all files Collapse all files

8
CHANGELOG
View file

@ -14,6 +14,10 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "synth -abc9" (experimental)
- Added "script -scriptwire
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels in synth_intel (e.g. bram -> map_bram)
- Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added automatic gzip decompression for frontends
- Added $_NMUX_ cell type
- Added automatic gzip compression (based on filename extension) for backends
@ -24,6 +28,10 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "synth_xilinx -ise" (experimental)
- Added "synth_xilinx -iopad"
- "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
- Improvements in pmgen: subpattern and recursive matches
- Added "opt_share" pass, run as part of "opt -full"
- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
- Removed "ice40_unlut"
Yosys 0.8 .. Yosys 0.8-dev
--------------------------