mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Converting a number of inline commands to refs

Browse source 
Also reflowing text for line width.
Maybe look into supporting commands with options?
This commit is contained in:
Krystine Sherwin 2023-08-08 12:45:18 +12:00
parent f8333e52f7
commit 685da6a2e5
No known key found for this signature in database
17 changed files with 398 additions and 384 deletions
Download patch file Download diff file Expand all files Collapse all files

57
docs/source/yosys_internals/formats/cell_library.rst
View file

@ -255,8 +255,8 @@ additional two parameters:
``\ARST_VALUE``
The state of ``\Q`` will be set to this value when the reset is active.
Usually these cells are generated by the ``proc`` pass using the information in
the designs RTLIL::Process objects.
Usually these cells are generated by the :cmd:ref:`proc` pass using the
information in the designs RTLIL::Process objects.
D-type flip-flops with synchronous reset are represented by ``$sdff`` cells. As
the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
@ -270,8 +270,8 @@ additional two parameters:
``\SRST_VALUE``
The state of ``\Q`` will be set to this value when the reset is active.
Note that the ``$adff`` and ``$sdff`` cells can only be used when the reset value is
constant.
Note that the ``$adff`` and ``$sdff`` cells can only be used when the reset
value is constant.
D-type flip-flops with asynchronous load are represented by ``$aldff`` cells. As
the ``$dff`` cells they have ``\CLK``, ``\D`` and ``\Q`` ports. In addition they
@ -433,16 +433,17 @@ The ``$memwr_v2`` cells have a clock input ``\CLK``, an enable input ``\EN``
``1'b1`` and on the negative edge if this parameter is ``1'b0``.
``\PORTID``
An identifier for this write port, used to index write port bit mask parameters.
An identifier for this write port, used to index write port bit mask
parameters.
``\PRIORITY_MASK``
This parameter is a bitmask of write ports that this write port has
priority over in case of writing to the same address. The bits of this
parameter are indexed by the other write port's ``\PORTID`` parameter.
Write ports can only have priority over write ports with lower port ID.
When two ports write to the same address and neither has priority over
the other, the result is undefined. Priority can only be set between
two synchronous ports sharing the same clock domain.
This parameter is a bitmask of write ports that this write port has priority
over in case of writing to the same address. The bits of this parameter are
indexed by the other write port's ``\PORTID`` parameter. Write ports can
only have priority over write ports with lower port ID. When two ports write
to the same address and neither has priority over the other, the result is
undefined. Priority can only be set between two synchronous ports sharing
the same clock domain.
The ``$meminit_v2`` cells have an address input ``\ADDR``, a data input
``\DATA``, with the width of the ``\DATA`` port equal to ``\WIDTH`` parameter
@ -468,13 +469,13 @@ synthesis to succeed.
initialization conflict.
The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
``$memrd_v2`` and ``$memwr_v2`` cells. The ``memory`` pass (i.e.~its various
sub-passes) migrates ``$dff`` cells into the ``$memrd_v2`` and ``$memwr_v2``
cells making them synchronous, then converts them to a single ``$mem_v2`` cell
and (optionally) maps this cell type to ``$dff`` cells for the individual words
and multiplexer-based address decoders for the read and write interfaces. When
the last step is disabled or not possible, a ``$mem_v2`` cell is left in the
design.
``$memrd_v2`` and ``$memwr_v2`` cells. The :cmd:ref:`memory` pass (i.e.~its
various sub-passes) migrates ``$dff`` cells into the ``$memrd_v2`` and
``$memwr_v2`` cells making them synchronous, then converts them to a single
``$mem_v2`` cell and (optionally) maps this cell type to ``$dff`` cells for the
individual words and multiplexer-based address decoders for the read and write
interfaces. When the last step is disabled or not possible, a ``$mem_v2`` cell
is left in the design.
The ``$mem_v2`` cell provides the following parameters:
@ -600,15 +601,15 @@ The ``$mem_v2`` cell has the following ports:
This input is ``\WR_PORTS*\WIDTH`` bits wide, containing all data
signals for the write ports.
The ``memory_collect`` pass can be used to convert discrete ``$memrd_v2``,
``$memwr_v2``, and ``$meminit_v2`` cells belonging to the same memory to a
single ``$mem_v2`` cell, whereas the ``memory_unpack`` pass performs the inverse
operation. The ``memory_dff`` pass can combine asynchronous memory ports that
are fed by or feeding registers into synchronous memory ports. The
``memory_bram`` pass can be used to recognize ``$mem_v2`` cells that can be
implemented with a block RAM resource on an FPGA. The ``memory_map`` pass can be
used to implement ``$mem_v2`` cells as basic logic: word-wide DFFs and address
decoders.
The :cmd:ref:`memory_collect` pass can be used to convert discrete
``$memrd_v2``, ``$memwr_v2``, and ``$meminit_v2`` cells belonging to the same
memory to a single ``$mem_v2`` cell, whereas the :cmd:ref:`memory_unpack` pass
performs the inverse operation. The :cmd:ref:`memory_dff` pass can combine
asynchronous memory ports that are fed by or feeding registers into synchronous
memory ports. The :cmd:ref:`memory_bram` pass can be used to recognize
``$mem_v2`` cells that can be implemented with a block RAM resource on an FPGA.
The :cmd:ref:`memory_map` pass can be used to implement ``$mem_v2`` cells as
basic logic: word-wide DFFs and address decoders.
Finite state machines
~~~~~~~~~~~~~~~~~~~~~