Converting a number of inline commands to refs

Also reflowing text for line width.
Maybe look into supporting commands with options?

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -407,9 +407,9 @@ transformed into a set of d-type flip-flops and the
 multiplexers.
 
 In more complex examples (e.g. asynchronous resets) the part of the
-``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree that describes the
-asynchronous reset must first be transformed to the correct
-``RTLIL::SyncRule`` objects. This is done by the proc_adff pass.
+``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree that describes the asynchronous
+reset must first be transformed to the correct ``RTLIL::SyncRule`` objects. This
+is done by the :cmd:ref:`proc_adff` pass.
 
 The ProcessGenerator algorithm
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -591,16 +591,16 @@ The proc pass
 
 The ProcessGenerator converts a behavioural model in AST representation to a
 behavioural model in ``RTLIL::Process`` representation. The actual conversion
-from a behavioural model to an RTL representation is performed by the ``proc``
-pass and the passes it launches:
+from a behavioural model to an RTL representation is performed by the
+:cmd:ref:`proc` pass and the passes it launches:
 
--  | proc_clean and proc_rmdead 
+-  | :cmd:ref:`proc_clean` and :cmd:ref:`proc_rmdead` 
    | These two passes just clean up the ``RTLIL::Process`` structure. The
-     ``proc_clean`` pass removes empty parts (eg. empty assignments) from the
-     process and ``proc_rmdead`` detects and removes unreachable branches from
-     the process's decision trees.
+     :cmd:ref:`proc_clean` pass removes empty parts (eg. empty assignments) from
+     the process and :cmd:ref:`proc_rmdead` detects and removes unreachable
+     branches from the process's decision trees.
 
--  | proc_arst 
+-  | :cmd:ref:`proc_arst` 
    | This pass detects processes that describe d-type flip-flops with
      asynchronous resets and rewrites the process to better reflect what they
      are modelling: Before this pass, an asynchronous reset has two
@@ -608,22 +608,22 @@ pass and the passes it launches:
      reset path. After this pass the sync rule for the reset is level-sensitive
      and the top-level ``RTLIL::SwitchRule`` has been removed.
 
--  | proc_mux 
+-  | :cmd:ref:`proc_mux` 
    | This pass converts the ``RTLIL::CaseRule``/ ``RTLIL::SwitchRule``-tree to a
      tree of multiplexers per written signal. After this, the ``RTLIL::Process``
      structure only contains the ``RTLIL::SyncRule`` s that describe the output
      registers.
 
--  | proc_dff
+-  | :cmd:ref:`proc_dff`
    | This pass replaces the ``RTLIL::SyncRule`` s to d-type flip-flops (with
      asynchronous resets if necessary).
 
--  | proc_dff
+-  | :cmd:ref:`proc_dff`
    | This pass replaces the ``RTLIL::MemWriteAction`` s with ``$memwr`` cells.
 
--  | proc_clean
-   | A final call to ``proc_clean`` removes the now empty ``RTLIL::Process``
-     objects.
+-  | :cmd:ref:`proc_clean`
+   | A final call to :cmd:ref:`proc_clean` removes the now empty
+     ``RTLIL::Process`` objects.
 
 Performing these last processing steps in passes instead of in the Verilog
 frontend has two important benefits: