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Converting a number of inline commands to refs
Also reflowing text for line width. Maybe look into supporting commands with options?
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@ -58,7 +58,7 @@ about the internal data storage format used in Yosys and the classes that it
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provides.
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This document will focus on the much simpler version of RTLIL left after the
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commands ``proc`` and ``memory`` (or ``memory -nomap``):
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commands :cmd:ref:`proc` and :cmd:ref:`memory` (or ``memory -nomap``):
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.. figure:: ../../images/simplified_rtlil.*
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:class: width-helper
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@ -77,9 +77,10 @@ It is possible to only work on this simpler version:
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}
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When trying to understand what a command does, creating a small test case to
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look at the output of ``dump`` and ``show`` before and after the command has
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been executed can be helpful. The :doc:`/using_yosys/more_scripting/selections`
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document has more information on using these commands.
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look at the output of :cmd:ref:`dump` and :cmd:ref:`show` before and after the
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command has been executed can be helpful. The
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:doc:`/using_yosys/more_scripting/selections` document has more information on
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using these commands.
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.. todo:: copypaste
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@ -120,15 +121,16 @@ Most commands modify existing modules, not create new ones.
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When modifying existing modules, stick to the following DOs and DON'Ts:
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- Do not remove wires. Simply disconnect them and let a successive ``clean``
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command worry about removing it.
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- Do not remove wires. Simply disconnect them and let a successive
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:cmd:ref:`clean` command worry about removing it.
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- Use ``module->fixup_ports()`` after changing the ``port_*`` properties of
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wires.
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- You can safely remove cells or change the ``connections`` property of a cell,
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but be careful when changing the size of the ``SigSpec`` connected to a cell
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port.
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- Use the ``SigMap`` helper class (see next slide) when you need a unique handle for each signal bit.
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- Use the ``SigMap`` helper class (see next section) when you need a unique
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handle for each signal bit.
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Using the SigMap helper class
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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