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Converting a number of inline commands to refs
Also reflowing text for line width. Maybe look into supporting commands with options?
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Krystine Sherwin
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685da6a2e5
17 changed files with 398 additions and 384 deletions
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@ -57,17 +57,17 @@ needed variations of parametric modules.
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hierarchy -check -top top_module
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The ``proc`` command
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~~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`proc` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Verilog frontend converts ``always``-blocks to RTL netlists for the
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expressions and "processess" for the control- and memory elements.
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The ``proc`` command transforms this "processess" to netlists of RTL multiplexer
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and register cells.
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The :cmd:ref:`proc` command transforms this "processess" to netlists of RTL
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multiplexer and register cells.
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The ``proc`` command is actually a macro-command that calls the following other
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commands:
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The :cmd:ref:`proc` command is actually a macro-command that calls the following
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other commands:
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.. code-block:: yoscrypt
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@ -80,8 +80,8 @@ commands:
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proc_clean # if all went fine, this should remove all the processes
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Many commands can not operate on modules with "processess" in them. Usually a
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call to ``proc`` is the first command in the actual synthesis procedure after
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design elaboration.
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call to :cmd:ref:`proc` is the first command in the actual synthesis procedure
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after design elaboration.
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Example
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^^^^^^^
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@ -120,11 +120,11 @@ Example
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:caption: ``docs/resources/PRESENTATION_ExSyn/proc_03.v``
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The ``opt`` command
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~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`opt` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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The ``opt`` command implements a series of simple optimizations. It also is a
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macro command that calls other commands:
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The :cmd:ref:`opt` command implements a series of simple optimizations. It also
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is a macro command that calls other commands:
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.. code-block:: yoscrypt
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@ -140,8 +140,8 @@ macro command that calls other commands:
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opt_expr # const folding and simple expression rewriting
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while [changed design]
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The command ``clean`` can be used as alias for ``opt_clean``. And ``;;`` can be
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used as shortcut for ``clean``. For example:
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The command :cmd:ref:`clean` can be used as alias for :cmd:ref:`opt_clean`. And
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``;;`` can be used as shortcut for :cmd:ref:`clean`. For example:
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.. code-block:: yoscrypt
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@ -195,31 +195,31 @@ Example
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:caption: ``docs/resources/PRESENTATION_ExSyn/opt_04.ys``
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When to use ``opt`` or ``clean``
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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When to use :cmd:ref:`opt` or :cmd:ref:`clean`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Usually it does not hurt to call ``opt`` after each regular command in the
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synthesis script. But it increases the synthesis time, so it is favourable to
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only call ``opt`` when an improvement can be achieved.
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Usually it does not hurt to call :cmd:ref:`opt` after each regular command in
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the synthesis script. But it increases the synthesis time, so it is favourable
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to only call :cmd:ref:`opt` when an improvement can be achieved.
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The designs in ``yosys-bigsim`` are a good playground for experimenting with the
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effects of calling ``opt`` in various places of the flow.
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effects of calling :cmd:ref:`opt` in various places of the flow.
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It generally is a good idea to call ``opt`` before inherently expensive commands
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such as ``sat`` or ``freduce``, as the possible gain is much higher in this
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cases as the possible loss.
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It generally is a good idea to call :cmd:ref:`opt` before inherently expensive
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commands such as :cmd:ref:`sat` or :cmd:ref:`freduce`, as the possible gain is
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much higher in this cases as the possible loss.
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The ``clean`` command on the other hand is very fast and many commands leave a
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mess (dangling signal wires, etc). For example, most commands do not remove any
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wires or cells. They just change the connections and depend on a later call to
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clean to get rid of the now unused objects. So the occasional ``;;`` is a good
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idea in every synthesis script.
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The :cmd:ref:`clean` command on the other hand is very fast and many commands
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leave a mess (dangling signal wires, etc). For example, most commands do not
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remove any wires or cells. They just change the connections and depend on a
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later call to clean to get rid of the now unused objects. So the occasional
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``;;`` is a good idea in every synthesis script.
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The ``memory`` command
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~~~~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`memory` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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In the RTL netlist, memory reads and writes are individual cells. This makes
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consolidating the number of ports for a memory easier. The ``memory``
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consolidating the number of ports for a memory easier. The :cmd:ref:`memory`
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transforms memories to an implementation. Per default that is logic for address
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decoders and registers. It also is a macro command that calls other commands:
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@ -269,12 +269,12 @@ Example
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:caption: ``docs/resources/PRESENTATION_ExSyn/memory_02.ys``
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The ``fsm`` command
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~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`fsm` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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The ``fsm`` command identifies, extracts, optimizes (re-encodes), and
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re-synthesizes finite state machines. It again is a macro that calls
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a series of other commands:
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The :cmd:ref:`fsm` command identifies, extracts, optimizes (re-encodes), and
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re-synthesizes finite state machines. It again is a macro that calls a series of
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other commands:
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.. code-block:: yoscrypt
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@ -298,26 +298,27 @@ a series of other commands:
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Some details on the most important commands from the ``fsm_*`` group:
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The ``fsm_detect`` command identifies FSM state registers and marks them with
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the ``(* fsm_encoding = "auto" *)`` attribute, if they do not have the
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The :cmd:ref:`fsm_detect` command identifies FSM state registers and marks them
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with the ``(* fsm_encoding = "auto" *)`` attribute, if they do not have the
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``fsm_encoding`` set already. Mark registers with ``(* fsm_encoding = "none"
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*)`` to disable FSM optimization for a register.
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The ``fsm_extract`` command replaces the entire FSM (logic and state registers)
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with a ``$fsm`` cell.
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The :cmd:ref:`fsm_extract` command replaces the entire FSM (logic and state
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registers) with a ``$fsm`` cell.
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The commands ``fsm_opt`` and ``fsm_recode`` can be used to optimize the FSM.
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The commands :cmd:ref:`fsm_opt` and :cmd:ref:`fsm_recode` can be used to
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optimize the FSM.
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Finally the ``fsm_map`` command can be used to convert the (optimized) ``$fsm``
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cell back to logic and registers.
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Finally the :cmd:ref:`fsm_map` command can be used to convert the (optimized)
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``$fsm`` cell back to logic and registers.
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The ``techmap`` command
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~~~~~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`techmap` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. figure:: ../../images/res/PRESENTATION_ExSyn/techmap_01.*
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:class: width-helper
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The ``techmap`` command replaces cells with implementations given as
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The :cmd:ref:`techmap` command replaces cells with implementations given as
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verilog source. For example implementing a 32 bit adder using 16 bit adders:
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
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@ -335,8 +336,9 @@ verilog source. For example implementing a 32 bit adder using 16 bit adders:
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stdcell mapping
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^^^^^^^^^^^^^^^
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When ``techmap`` is used without a map file, it uses a built-in map file to map
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all RTL cell types to a generic library of built-in logic gates and registers.
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When :cmd:ref:`techmap` is used without a map file, it uses a built-in map file
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to map all RTL cell types to a generic library of built-in logic gates and
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registers.
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The built-in logic gate types are: ``$_NOT_``, ``$_AND_``, ``$_OR_``,
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``$_XOR_``, and ``$_MUX_``.
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@ -351,26 +353,27 @@ The register types are: ``$_SR_NN_``, ``$_SR_NP_``, ``$_SR_PN_``, ``$_SR_PP_``,
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See :doc:`/yosys_internals/formats/cell_library` for more about the internal
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cells used.
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The ``abc`` command
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~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`abc` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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The ``abc`` command provides an interface to ABC_, an open source tool for
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low-level logic synthesis.
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The :cmd:ref:`abc` command provides an interface to ABC_, an open source tool
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for low-level logic synthesis.
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.. _ABC: http://www.eecs.berkeley.edu/~alanmi/abc/
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The ``abc`` command processes a netlist of internal gate types and can perform:
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The :cmd:ref:`abc` command processes a netlist of internal gate types and can
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perform:
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- logic minimization (optimization)
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- mapping of logic to standard cell library (liberty format)
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- mapping of logic to k-LUTs (for FPGA synthesis)
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Optionally ``abc`` can process registers from one clock domain and perform
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sequential optimization (such as register balancing).
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Optionally :cmd:ref:`abc` can process registers from one clock domain and
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perform sequential optimization (such as register balancing).
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ABC is also controlled using scripts. An ABC script can be specified to use more
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advanced ABC features. It is also possible to write the design with
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``write_blif`` and load the output file into ABC outside of Yosys.
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:cmd:ref:`write_blif` and load the output file into ABC outside of Yosys.
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Example
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^^^^^^^
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@ -389,16 +392,16 @@ Example
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Other special-purpose mapping commands
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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``dfflibmap``
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:cmd:ref:`dfflibmap`
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This command maps the internal register cell types to the register types
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described in a liberty file.
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``hilomap``
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:cmd:ref:`hilomap`
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Some architectures require special driver cells for driving a constant hi or
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lo value. This command replaces simple constants with instances of such driver
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cells.
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``iopadmap``
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:cmd:ref:`iopadmap`
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Top-level input/outputs must usually be implemented using special I/O-pad
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cells. This command inserts this cells to the design.
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@ -436,5 +439,6 @@ Example Synthesis Script
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# write synthesis results
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write_edif synth.edif
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The weird ``select`` expressions at the end of this script are discussed later
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in :doc:`using_yosys/more_scripting/selections</using_yosys/more_scripting/selections>`.
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The weird :cmd:ref:`select` expressions at the end of this script are discussed
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later in
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:doc:`using_yosys/more_scripting/selections</using_yosys/more_scripting/selections>`.
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