mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 10:05:33 +00:00
Code Activity

Converting a number of inline commands to refs

Browse source 
Also reflowing text for line width.
Maybe look into supporting commands with options?
This commit is contained in:
Krystine Sherwin 2023-08-08 12:45:18 +12:00
parent f8333e52f7
commit 685da6a2e5
No known key found for this signature in database
17 changed files with 398 additions and 384 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst
View file

@ -235,8 +235,8 @@ signal is connected throughout the whole design hierarchy.
endmodule
In line 18 the ``proc`` command is called. But in this script the signal name
globrst is passed to the command as a global reset signal for resetting the
In line 18 the :cmd:ref:`proc` command is called. But in this script the signal
name globrst is passed to the command as a global reset signal for resetting the
registers to their assigned initial values.
Finally in line 19 the techmap command is used to replace all instances of