From 10a814f97808de8cce7e50a03f01832db66c263e Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Fri, 17 Apr 2020 06:16:59 +0000 Subject: [PATCH 1/2] Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes. --- frontends/verilog/verilog_parser.y | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 7447ab8d5..f762f9025 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1924,11 +1924,13 @@ always_events: always_event: TOK_POSEDGE expr { AstNode *node = new AstNode(AST_POSEDGE); + SET_AST_NODE_LOC(node, @1, @1); ast_stack.back()->children.push_back(node); node->children.push_back($2); } | TOK_NEGEDGE expr { AstNode *node = new AstNode(AST_NEGEDGE); + SET_AST_NODE_LOC(node, @1, @1); ast_stack.back()->children.push_back(node); node->children.push_back($2); } | From 00d74f0b9ceecc7b60f50fddb3b6ab0c47701923 Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Fri, 17 Apr 2020 06:23:03 +0000 Subject: [PATCH 2/2] Set Verilog source location for explicit blocks (`begin` ... `end`). --- frontends/verilog/verilog_parser.y | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index f762f9025..4a5aba79e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2246,6 +2246,7 @@ behavioral_stmt: exitTypeScope(); if ($4 != NULL && $8 != NULL && *$4 != *$8) frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1); + SET_AST_NODE_LOC(ast_stack.back(), @2, @8); delete $4; delete $8; ast_stack.pop_back();