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Fix padding, remove CIs from undriven_bits before erasing undriven POs

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This commit is contained in:
Eddie Hung 2019-05-26 11:26:38 -07:00
parent 086b6560b4
commit 67f7c64a77
1 changed files with 8 additions and 14 deletions
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22
backends/aiger/xaiger.cc
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@ -302,16 +302,13 @@ struct XAigerWriter
continue; continue;
// Fully pad all unused input connections of this box cell with S0 // Fully pad all unused input connections of this box cell with S0
// Fully pad all undriven output connections of thix box cell with anonymous wires // Fully pad all undriven output connections of this box cell with anonymous wires
for (const auto w : box_module->wires()) { for (const auto w : box_module->wires()) {
if (w->port_input) { if (w->port_input) {
auto it = cell->connections_.find(w->name); auto it = cell->connections_.find(w->name);
if (it != cell->connections_.end()) { if (it != cell->connections_.end()) {
if (GetSize(it->second) < GetSize(w)) { if (GetSize(it->second) < GetSize(w))
RTLIL::SigSpec padded_connection(RTLIL::S0, GetSize(w)-GetSize(it->second)); it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
padded_connection.append(it->second);
it->second = std::move(padded_connection);
}
} }
else else
cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w)); cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
@ -319,11 +316,8 @@ struct XAigerWriter
if (w->port_output) { if (w->port_output) {
auto it = cell->connections_.find(w->name); auto it = cell->connections_.find(w->name);
if (it != cell->connections_.end()) { if (it != cell->connections_.end()) {
if (GetSize(it->second) < GetSize(w)) { if (GetSize(it->second) < GetSize(w))
RTLIL::SigSpec padded_connection = module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)); it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
padded_connection.append(it->second);
it->second = std::move(padded_connection);
}
} }
else else
cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w)); cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w));
@ -384,13 +378,13 @@ struct XAigerWriter
} }
// Do some CI/CO post-processing: // Do some CI/CO post-processing:
// CIs cannot be undriven
for (const auto &c : ci_bits)
undriven_bits.erase(c.first);
// Erase all POs that are undriven // Erase all POs that are undriven
if (!holes_mode) if (!holes_mode)
for (auto bit : undriven_bits) for (auto bit : undriven_bits)
output_bits.erase(bit); output_bits.erase(bit);
// CIs cannot be undriven
for (const auto &c : ci_bits)
undriven_bits.erase(c.first);
for (auto bit : unused_bits) for (auto bit : unused_bits)
undriven_bits.erase(bit); undriven_bits.erase(bit);