mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Replace std::set with pool for handled_cells and techmap_wire_names.

Browse source
This commit is contained in:
Alberto Gonzalez 2020-04-19 22:24:20 +00:00
parent 64c16f8c13
commit 67f4046c05
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
passes/techmap/techmap.cc
View file

@ -463,7 +463,7 @@ struct TechmapWorker
} }
} }
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells, bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
const std::map<IdString, std::set<IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion) const std::map<IdString, std::set<IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
{ {
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
@ -805,7 +805,7 @@ struct TechmapWorker
bool keep_running = true; bool keep_running = true;
techmap_do_cache[tpl] = true; techmap_do_cache[tpl] = true;
std::set<IdString> techmap_wire_names; pool<IdString> techmap_wire_names;
while (keep_running) while (keep_running)
{ {
@ -1324,7 +1324,7 @@ struct TechmapPass : public Pass {
int module_max_iter = max_iter; int module_max_iter = max_iter;
bool did_something = true; bool did_something = true;
std::set<RTLIL::Cell*> handled_cells; pool<RTLIL::Cell*> handled_cells;
while (did_something) { while (did_something) {
did_something = false; did_something = false;
if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false)) if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
@ -1391,7 +1391,7 @@ struct FlattenPass : public Pass {
if (mod->get_bool_attribute(ID::top)) if (mod->get_bool_attribute(ID::top))
top_mod = mod; top_mod = mod;
std::set<RTLIL::Cell*> handled_cells; pool<RTLIL::Cell*> handled_cells;
if (top_mod != nullptr) { if (top_mod != nullptr) {
worker.flatten_do_list.insert(top_mod->name); worker.flatten_do_list.insert(top_mod->name);
while (!worker.flatten_do_list.empty()) { while (!worker.flatten_do_list.empty()) {