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Make scopeinfo not default
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parent
e093ac5bca
commit
6795c32167
1 changed files with 7 additions and 7 deletions
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@ -58,7 +58,7 @@ void map_sigspec(const dict<RTLIL::Wire*, RTLIL::Wire*> &map, RTLIL::SigSpec &si
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struct FlattenWorker
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{
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bool ignore_wb = false;
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bool create_scopeinfo = true;
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bool create_scopeinfo = false; // SILIMATE: default false
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bool create_scopename = false;
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template<class T>
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@ -331,12 +331,12 @@ struct FlattenPass : public Pass {
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log(" -wb\n");
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log(" Ignore the 'whitebox' attribute on cell implementations.\n");
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log("\n");
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log(" -noscopeinfo\n");
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log(" Do not create '$scopeinfo' cells that preserve attributes of cells and\n");
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log(" modules that were removed during flattening. With this option, the\n");
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log(" -scopeinfo\n");
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log(" Create '$scopeinfo' cells that preserve attributes of cells and\n");
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log(" modules that were removed during flattening. Without this option, the\n");
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log(" 'src' attribute of a given cell is merged into all objects replacing\n");
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log(" that cell, with multiple distinct 'src' locations separated by '|'.\n");
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log(" Without this option these 'src' locations can be found via the\n");
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log(" With this option these 'src' locations can be found via the\n");
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log(" cell_src' and 'module_src' attribute of '$scopeinfo' cells.\n");
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log("\n");
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log(" -scopename\n");
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@ -359,8 +359,8 @@ struct FlattenPass : public Pass {
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worker.ignore_wb = true;
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continue;
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}
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if (args[argidx] == "-noscopeinfo") {
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worker.create_scopeinfo = false;
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if (args[argidx] == "-scopeinfo") {
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worker.create_scopeinfo = true;
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continue;
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}
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if (args[argidx] == "-scopename") {
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