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flatten: simplify. NFC.

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The `design` and `map` designs are always the same when flattening.
This commit is contained in:
whitequark 2020-06-03 01:19:55 +00:00
parent 9338ff66b9
commit 6783876807
1 changed files with 8 additions and 8 deletions
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16
passes/techmap/flatten.cc
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@ -251,7 +251,7 @@ struct FlattenWorker
} }
} }
bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells, bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Cell*> &handled_cells,
const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion) const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion)
{ {
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
@ -283,7 +283,7 @@ struct FlattenWorker
bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
for (auto &tpl_name : celltypeMap.at(cell_type)) for (auto &tpl_name : celltypeMap.at(cell_type))
if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) if (design->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy))
keepit = true; keepit = true;
if (keepit) { if (keepit) {
if (!flatten_keep_list[cell]) { if (!flatten_keep_list[cell]) {
@ -304,7 +304,7 @@ struct FlattenWorker
continue; continue;
for (auto &tpl_name : celltypeMap.at(cell_type)) { for (auto &tpl_name : celltypeMap.at(cell_type)) {
RTLIL::Module *tpl = map->module(tpl_name); RTLIL::Module *tpl = design->module(tpl_name);
RTLIL::Wire *port = tpl->wire(conn.first); RTLIL::Wire *port = tpl->wire(conn.first);
if (port && port->port_input) if (port && port->port_input)
cell_to_inbit[cell].insert(sig.begin(), sig.end()); cell_to_inbit[cell].insert(sig.begin(), sig.end());
@ -337,7 +337,7 @@ struct FlattenWorker
for (auto &tpl_name : celltypeMap.at(cell_type)) for (auto &tpl_name : celltypeMap.at(cell_type))
{ {
IdString derived_name = tpl_name; IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->module(tpl_name); RTLIL::Module *tpl = design->module(tpl_name);
dict<IdString, RTLIL::Const> parameters(cell->parameters); dict<IdString, RTLIL::Const> parameters(cell->parameters);
if (tpl->get_blackbox_attribute(ignore_wb)) if (tpl->get_blackbox_attribute(ignore_wb))
@ -350,8 +350,8 @@ struct FlattenWorker
} else { } else {
if (parameters.size() != 0) { if (parameters.size() != 0) {
mkdebug.on(); mkdebug.on();
derived_name = tpl->derive(map, parameters); derived_name = tpl->derive(design, parameters);
tpl = map->module(derived_name); tpl = design->module(derived_name);
log_continue = true; log_continue = true;
} }
cache.emplace(std::move(key), tpl); cache.emplace(std::move(key), tpl);
@ -442,13 +442,13 @@ struct FlattenPass : public Pass {
worker.flatten_do_list.insert(top_mod->name); worker.flatten_do_list.insert(top_mod->name);
while (!worker.flatten_do_list.empty()) { while (!worker.flatten_do_list.empty()) {
auto mod = design->module(*worker.flatten_do_list.begin()); auto mod = design->module(*worker.flatten_do_list.begin());
while (worker.flatten_module(design, mod, design, handled_cells, celltypeMap, false)) { } while (worker.flatten_module(design, mod, handled_cells, celltypeMap, false)) { }
worker.flatten_done_list.insert(mod->name); worker.flatten_done_list.insert(mod->name);
worker.flatten_do_list.erase(mod->name); worker.flatten_do_list.erase(mod->name);
} }
} else { } else {
for (auto mod : design->modules().to_vector()) for (auto mod : design->modules().to_vector())
while (worker.flatten_module(design, mod, design, handled_cells, celltypeMap, false)) { } while (worker.flatten_module(design, mod, handled_cells, celltypeMap, false)) { }
} }
log_suppressed(); log_suppressed();