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xilinx: Add support for UltraScale[+] BRAM mapping

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-10-18 13:24:19 +01:00
parent f02623abb5
commit 6769d31ddb
7 changed files with 1062 additions and 416 deletions
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7
techlibs/xilinx/synth_xilinx.cc
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@ -305,6 +305,8 @@ struct SynthXilinxPass : public ScriptPass
run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
} else if (family == "xc6v" || family == "xc7") {
run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
} else if (family == "xcu" || family == "xcup") {
run("read_verilog -lib +/xilinx/xcu_brams_bb.v");
}
run(stringf("hierarchy -check %s", top_opt.c_str()));
@ -417,8 +419,11 @@ struct SynthXilinxPass : public ScriptPass
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
run("techmap -map +/xilinx/xc6s_brams_map.v");
} else if (family == "xc6v" || family == "xc7") {
run("memory_bram -rules +/xilinx/xc7_brams.txt");
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
run("techmap -map +/xilinx/xc7_brams_map.v");
} else if (family == "xcu" || family == "xcup") {
run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt");
run("techmap -map +/xilinx/xcu_brams_map.v");
} else {
log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
}