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xilinx: Add support for UltraScale[+] BRAM mapping

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-10-18 13:24:19 +01:00
parent f02623abb5
commit 6769d31ddb
7 changed files with 1062 additions and 416 deletions
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22
techlibs/xilinx/cells_xtra.py
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@ -228,8 +228,8 @@ XC6V_CELLS = [
# Cell('FDSE'),
Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
Cell('LDCE'),
Cell('LDPE'),
# Cell('LDCE'),
# Cell('LDPE'),
Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
# Slice/CLB primitives.
@ -378,8 +378,8 @@ XC7_CELLS = [
# Cell('FDSE'),
Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
Cell('LDCE'),
Cell('LDPE'),
# Cell('LDCE'),
# Cell('LDPE'),
Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
# Slice/CLB primitives.
@ -435,8 +435,8 @@ XCU_CELLS = [
# Blockram.
Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
#Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
#Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}),
Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
@ -491,6 +491,12 @@ XCU_CELLS = [
Cell('PLLE3_BASE'),
Cell('PLLE4_ADV'),
Cell('PLLE4_BASE'),
# the "E2" variants are not strictly speaking UltraScale[+] cells
# but are automatically upgraded for backwards compatibility purposes
Cell('MMCME2_ADV'),
Cell('MMCME2_BASE'),
Cell('PLLE2_ADV'),
Cell('PLLE2_BASE'),
# Configuration.
Cell('BSCANE2', keep=True),
@ -562,8 +568,8 @@ XCU_CELLS = [
# Cell('FDSE'),
Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}),
Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
Cell('LDCE'),
Cell('LDPE'),
# Cell('LDCE'),
# Cell('LDPE'),
Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
# NOTE: not in the official library guide!