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Be slightly less aggressive in "deminout" pass

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-19 14:29:38 +02:00
parent 25c5002f83
commit 675a44b41a
1 changed files with 28 additions and 4 deletions
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32
passes/techmap/deminout.cc
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@ -57,7 +57,7 @@ struct DeminoutPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
SigMap sigmap(module); SigMap sigmap(module);
pool<SigBit> bits_written, bits_used, bits_inout; pool<SigBit> bits_written, bits_used, bits_inout, bits_tribuf;
dict<SigBit, int> bits_numports; dict<SigBit, int> bits_numports;
for (auto wire : module->wires()) for (auto wire : module->wires())
@ -82,6 +82,25 @@ struct DeminoutPass : public Pass {
if (cellport_in) if (cellport_in)
for (auto bit : sigmap(conn.second)) for (auto bit : sigmap(conn.second))
bits_used.insert(bit); bits_used.insert(bit);
if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_"))
{
bool tribuf = (cell->type == "$_TBUF_");
if (!tribuf) {
for (auto &c : cell->connections()) {
if (!c.first.in("\\A", "\\B"))
continue;
for (auto b : sigmap(c.second))
if (b == State::Sz)
tribuf = true;
}
}
if (tribuf)
for (auto bit : sigmap(conn.second))
bits_tribuf.insert(bit);
}
} }
for (auto wire : module->selected_wires()) for (auto wire : module->selected_wires())
@ -95,10 +114,15 @@ struct DeminoutPass : public Pass {
if (bits_numports[bit] > 1 || bits_inout.count(bit)) if (bits_numports[bit] > 1 || bits_inout.count(bit))
new_input = true, new_output = true; new_input = true, new_output = true;
if (bits_written.count(bit)) if (bits_written.count(bit)) {
new_output = true; new_output = true;
else if (bits_used.count(bit)) if (bits_tribuf.count(bit))
new_input = true; goto tribuf_bit;
} else {
tribuf_bit:
if (bits_used.count(bit))
new_input = true;
}
} }
if (new_input != new_output) { if (new_input != new_output) {