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https://github.com/YosysHQ/yosys
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rewrite functional backend test code in python
This commit is contained in:
Emily Schmidt
parent
9ad859fc0a
commit
674e6d201d
57 changed files with 554 additions and 1238 deletions
275
tests/functional/rtlil_cells.py
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275
tests/functional/rtlil_cells.py
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from itertools import chain
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import random
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widths = [
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(16, 32, 48, True),
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(16, 32, 48, False),
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(32, 16, 48, True),
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(32, 16, 48, False),
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(32, 32, 16, True),
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(32, 32, 16, False)
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]
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shift_widths = [
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(32, 6, 32, True, False),
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(32, 6, 32, False, False),
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(32, 6, 64, True, False),
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(32, 6, 64, False, False),
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(32, 32, 16, True, False),
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(32, 32, 16, False, False),
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(32, 6, 32, True, True),
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(32, 6, 32, False, True),
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(32, 6, 64, True, True),
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(32, 6, 64, False, True),
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(32, 32, 16, True, True),
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(32, 32, 16, False, True),
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]
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def write_rtlil_cell(f, cell_type, inputs, outputs, parameters):
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f.write('autoidx 1\n')
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f.write('module \\gold\n')
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idx = 1
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for name, width in inputs.items():
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f.write(f'\twire width {width} input {idx} \\{name}\n')
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idx += 1
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for name, width in outputs.items():
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f.write(f'\twire width {width} output {idx} \\{name}\n')
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idx += 1
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f.write(f'\tcell ${cell_type} \\UUT\n')
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for (name, value) in parameters.items():
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f.write(f'\t\tparameter \\{name} {value}\n')
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for name in chain(inputs.keys(), outputs.keys()):
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f.write(f'\t\tconnect \\{name} \\{name}\n')
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f.write(f'\tend\nend\n')
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class BaseCell:
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def __init__(self, name):
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self.name = name
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class UnaryCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, _, y_width, signed) in widths:
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yield (f'{a_width}-{y_width}-{'S' if signed else 'U'}',
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{'A_WIDTH' : a_width,
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'A_SIGNED' : int(signed),
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'Y_WIDTH' : y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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class BinaryCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, b_width, y_width, signed) in widths:
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yield (f'{a_width}-{b_width}-{y_width}-{'S' if signed else 'U'}',
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{'A_WIDTH' : a_width,
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'A_SIGNED' : int(signed),
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'B_WIDTH' : b_width,
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'B_SIGNED' : int(signed),
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'Y_WIDTH' : y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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class ShiftCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, b_width, y_width, a_signed, b_signed) in shift_widths:
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if not self.name in ('shift', 'shiftx') and b_signed: continue
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if self.name == 'shiftx' and a_signed: continue
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yield (f'{a_width}-{b_width}-{y_width}-{'S' if a_signed else 'U'}{'S' if b_signed else 'U'}',
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{'A_WIDTH' : a_width,
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'A_SIGNED' : int(a_signed),
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'B_WIDTH' : b_width,
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'B_SIGNED' : int(b_signed),
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'Y_WIDTH' : y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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class MuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for width in [10, 20, 40]:
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yield (f'{width}', {'WIDTH' : width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': parameters['WIDTH'], 'S': 1}, {'Y': parameters['WIDTH']}, parameters)
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class BWCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for width in [10, 20, 40]:
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yield (f'{width}', {'WIDTH' : width})
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def write_rtlil_file(self, f, parameters):
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inputs = {'A': parameters['WIDTH'], 'B': parameters['WIDTH']}
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if self.name == "bwmux": inputs['S'] = parameters['WIDTH']
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write_rtlil_cell(f, self.name, inputs, {'Y': parameters['WIDTH']}, parameters)
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class PMuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (width, s_width) in [(10, 1), (10, 4), (20, 4)]:
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yield (f'{width}-{s_width}',
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{'WIDTH' : width,
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'S_WIDTH' : s_width})
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def write_rtlil_file(self, f, parameters):
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s_width = parameters['S_WIDTH']
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b_width = parameters['WIDTH'] * s_width
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': b_width, 'S': s_width}, {'Y': parameters['WIDTH']}, parameters)
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class BMuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (width, s_width) in [(10, 1), (10, 2), (10, 4)]:
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yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'] << parameters['S_WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH']}, parameters)
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class DemuxCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (width, s_width) in [(10, 1), (32, 2), (16, 4)]:
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yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH'] << parameters['S_WIDTH']}, parameters)
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def seeded_randint(seed, a, b):
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r = random.getstate()
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random.seed(seed)
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n = random.randint(a, b)
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random.setstate(r)
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return n
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class LUTCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for width in [4, 6, 8]:
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lut = seeded_randint(width, 0, 2**width - 1)
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yield (f'{width}', {'WIDTH' : width, 'LUT' : lut})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['WIDTH']}, {'Y': 1}, parameters)
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class ConcatCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, b_width) in [(16, 16), (8, 14), (20, 10)]:
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yield (f'{a_width}-{b_width}', {'A_WIDTH' : a_width, 'B_WIDTH' : b_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B' : parameters['B_WIDTH']}, {'Y': parameters['A_WIDTH'] + parameters['B_WIDTH']}, parameters)
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class SliceCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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for (a_width, offset, y_width) in [(32, 10, 15), (8, 0, 4), (10, 0, 10)]:
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yield (f'{a_width}-{offset}-{y_width}', {'A_WIDTH' : a_width, 'OFFSET' : offset, 'Y_WIDTH': y_width})
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def write_rtlil_file(self, f, parameters):
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write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters)
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class FailCell(BaseCell):
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def __init__(self, name):
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super().__init__(name)
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def generate_tests(self):
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yield ('', {})
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def write_rtlil_file(self, f, parameters):
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raise Exception(f'\'{self.name}\' cell unimplemented in test generator')
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rtlil_cells = [
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UnaryCell("not"),
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UnaryCell("pos"),
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UnaryCell("neg"),
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BinaryCell("and"),
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BinaryCell("or"),
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BinaryCell("xor"),
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BinaryCell("xnor"),
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UnaryCell("reduce_and"),
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UnaryCell("reduce_or"),
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UnaryCell("reduce_xor"),
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UnaryCell("reduce_xnor"),
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UnaryCell("reduce_bool"),
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ShiftCell("shl"),
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ShiftCell("shr"),
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ShiftCell("sshl"),
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ShiftCell("sshr"),
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ShiftCell("shift"),
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ShiftCell("shiftx"),
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# ("fa", ["A", "B", "C", "X", "Y"]),
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# ("lcu", ["P", "G", "CI", "CO"]),
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# ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]),
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BinaryCell("lt"),
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BinaryCell("le"),
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BinaryCell("eq"),
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BinaryCell("ne"),
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BinaryCell("eqx"),
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BinaryCell("nex"),
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BinaryCell("ge"),
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BinaryCell("gt"),
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BinaryCell("add"),
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BinaryCell("sub"),
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BinaryCell("mul"),
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# BinaryCell("macc"),
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BinaryCell("div"),
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BinaryCell("mod"),
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BinaryCell("divfloor"),
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BinaryCell("modfloor"),
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BinaryCell("pow"),
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UnaryCell("logic_not"),
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BinaryCell("logic_and"),
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BinaryCell("logic_or"),
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SliceCell("slice"),
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ConcatCell("concat"),
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MuxCell("mux"),
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BMuxCell("bmux"),
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PMuxCell("pmux"),
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DemuxCell("demux"),
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LUTCell("lut"),
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# ("sop", ["A", "Y"]),
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# ("tribuf", ["A", "EN", "Y"]),
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# ("specify2", ["EN", "SRC", "DST"]),
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# ("specify3", ["EN", "SRC", "DST", "DAT"]),
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# ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]),
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BWCell("bweqx"),
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BWCell("bwmux"),
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# ("assert", ["A", "EN"]),
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# ("assume", ["A", "EN"]),
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# ("live", ["A", "EN"]),
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# ("fair", ["A", "EN"]),
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# ("cover", ["A", "EN"]),
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# ("initstate", ["Y"]),
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# ("anyconst", ["Y"]),
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# ("anyseq", ["Y"]),
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# ("anyinit", ["D", "Q"]),
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# ("allconst", ["Y"]),
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# ("allseq", ["Y"]),
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# ("equiv", ["A", "B", "Y"]),
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# ("print", ["EN", "TRG", "ARGS"]),
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# ("check", ["A", "EN", "TRG", "ARGS"]),
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# ("set_tag", ["A", "SET", "CLR", "Y"]),
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# ("get_tag", ["A", "Y"]),
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# ("overwrite_tag", ["A", "SET", "CLR"]),
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# ("original_tag", ["A", "Y"]),
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# ("future_ff", ["A", "Y"]),
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# ("scopeinfo", []),
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]
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def generate_test_cases(per_cell):
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tests = []
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names = []
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for cell in rtlil_cells:
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seen_names = set()
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for (name, parameters) in cell.generate_tests():
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if not name in seen_names:
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seen_names.add(name)
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tests.append((cell, parameters))
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names.append(f'{cell.name}-{name}' if name != '' else cell.name)
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if per_cell is not None and len(seen_names) >= per_cell:
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break
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return (names, tests)
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