From 32e96605d468b632d3c51a0286b199a3ed5043a4 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 19 Jan 2026 02:44:54 +0000 Subject: [PATCH] Don't update `used_signals` for retained wires in `rmunused_module_signals`. These updates should not be necessary. In fact, if they were necessary, this code would be buggy, because the results would depend on the order in which wires are traversed: If wire A is retained, which causes an update to `used_signals`, which then causes wire B to be retained when it otherwise wouldn't be, then we would get different results depending on whether A is visited before B. These updates will also make it difficult to process these wires in parallel. --- passes/opt/opt_clean.cc | 2 -- tests/opt/opt_clean_standalone_wires.ys | 10 ++++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) create mode 100644 tests/opt/opt_clean_standalone_wires.ys diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3892c7581..76f425099 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -467,8 +467,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes.erase(ID::init); else wire->attributes.at(ID::init) = initval; - used_signals.add(new_conn.first); - used_signals.add(new_conn.second); module->connect(new_conn); } diff --git a/tests/opt/opt_clean_standalone_wires.ys b/tests/opt/opt_clean_standalone_wires.ys new file mode 100644 index 000000000..d6716d725 --- /dev/null +++ b/tests/opt/opt_clean_standalone_wires.ys @@ -0,0 +1,10 @@ +read_rtlil << EOT +module \test + wire \wire_a + wire \wire_f + connect \wire_f \wire_a +end +EOT + +opt_clean +select -assert-count 0 */*