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fix proc, reduce warnings

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This commit is contained in:
Emil J. Tywoniak 2024-06-21 11:56:36 +02:00
parent 1be8f8023a
commit 66c629374c
3 changed files with 3 additions and 3 deletions
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2
passes/cmds/glift.cc
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@ -343,7 +343,7 @@ private:
//recurse to GLIFT model the child module. However, we need to augment the ports list
//with taint signals and connect the new ports to the corresponding taint signals.
RTLIL::Module *cell_module_def = module->design->module(cell->type);
auto orig_ports = cell->connections();
auto orig_ports = cell->connections().as_dict();
log("Adding cell %s\n", cell_module_def->name.c_str());
for (auto &&it : orig_ports) {
RTLIL::SigSpec port = it.second;