Improved FSM one-hot encoding, added binary encoding

passes/fsm/fsm.cc

@@ -56,6 +56,7 @@ struct FsmPass : public Pass {
 		log("    -expand, -norecode, -export, -nomap\n");
 		log("        enable or disable passes as indicated above\n");
 		log("\n");
+		log("    -encoding tye\n");
 		log("    -fm_set_fsm_file file\n");
 		log("        passed through to fsm_recode pass\n");
 		log("\n");
@@ -67,6 +68,7 @@ struct FsmPass : public Pass {
 		bool flag_expand = false;
 		bool flag_export = false;
 		std::string fm_set_fsm_file_opt;
+		std::string encoding_opt;
 
 		log_header("Executing FSM pass (extract and optimize FSM).\n");
 		log_push();
@@ -78,6 +80,10 @@ struct FsmPass : public Pass {
 				fm_set_fsm_file_opt = " -fm_set_fsm_file " + args[++argidx];
 				continue;
 			}
+			if (arg == "-encoding" && argidx+1 < args.size() && fm_set_fsm_file_opt.empty()) {
+				encoding_opt = " -encoding " + args[++argidx];
+				continue;
+			}
 			if (arg == "-norecode") {
 				flag_norecode = true;
 				continue;
@@ -112,7 +118,7 @@ struct FsmPass : public Pass {
 		}
 
 		if (!flag_norecode)
-			Pass::call(design, "fsm_recode" + fm_set_fsm_file_opt);
+			Pass::call(design, "fsm_recode" + fm_set_fsm_file_opt + encoding_opt);
 		Pass::call(design, "fsm_info");
 
 		if (!flag_nomap)

passes/fsm/fsm_map.cc

@@ -77,27 +77,30 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			and_sig.append(RTLIL::SigSpec(eq_wire));
 		}
 
-		if (or_sig.width == 1)
+		if (or_sig.width < num_states-int(fullstate_cache.size()))
 		{
-			and_sig.append(or_sig);
+			if (or_sig.width == 1)
-		}
+			{
-		else if (or_sig.width < num_states && int(it.second.size()) < num_states)
+				and_sig.append(or_sig);
-		{
+			}
-			RTLIL::Wire *or_wire = new RTLIL::Wire;
+			else
-			or_wire->name = NEW_ID;
+			{
-			module->add(or_wire);
+				RTLIL::Wire *or_wire = new RTLIL::Wire;
+				or_wire->name = NEW_ID;
+				module->add(or_wire);
 
-			RTLIL::Cell *or_cell = new RTLIL::Cell;
+				RTLIL::Cell *or_cell = new RTLIL::Cell;
-			or_cell->name = NEW_ID;
+				or_cell->name = NEW_ID;
-			or_cell->type = "$reduce_or";
+				or_cell->type = "$reduce_or";
-			or_cell->connections["\\A"] = or_sig;
+				or_cell->connections["\\A"] = or_sig;
-			or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire);
+				or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire);
-			or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
+				or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
-			or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.width);
+				or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.width);
-			or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+				or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			module->add(or_cell);
+				module->add(or_cell);
 
-			and_sig.append(RTLIL::SigSpec(or_wire));
+				and_sig.append(RTLIL::SigSpec(or_wire));
+			}
 		}
 
 		switch (and_sig.width)
@@ -131,7 +134,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			cases_vector.append(RTLIL::SigSpec(1, 1));
 			break;
 		default:
-			assert(!"This should never happen!");
+			log_abort();
 		}
 	}
 
@@ -184,6 +187,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		state_dff->type = "$adff";
 		state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"];
 		state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state];
+		for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
+			if (bit != RTLIL::State::S1)
+				bit = RTLIL::State::S0;
 		state_dff->connections["\\ARST"] = fsm_cell->connections["\\ARST"];
 	}
 	state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
@@ -221,8 +227,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		}
 		else
 		{
-			if (sig_b.as_bool() || sig_b.width != fsm_data.state_bits)
+			encoding_is_onehot = false;
-				encoding_is_onehot = false;
 
 			RTLIL::Cell *eq_cell = new RTLIL::Cell;
 			eq_cell->name = NEW_ID;
@@ -266,6 +271,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
 	if (encoding_is_onehot)
 	{
+		RTLIL::SigSpec next_state_sig(RTLIL::State::Sm, next_state_wire->width);
 		for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
 			RTLIL::Const state = fsm_data.state_table[i];
 			int bit_idx = -1;
@@ -273,8 +279,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 				if (state.bits[j] == RTLIL::State::S1)
 					bit_idx = j;
 			if (bit_idx >= 0)
-				module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(next_state_wire, 1, bit_idx), RTLIL::SigSpec(next_state_onehot, 1, i)));
+				next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, 1, i));
 		}
+		log_assert(!next_state_sig.has_marked_bits());
+		module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig));
 	}
 	else
 	{

passes/fsm/fsm_recode.cc

@@ -23,6 +23,7 @@
 #include "kernel/consteval.h"
 #include "kernel/celltypes.h"
 #include "fsmdata.h"
+#include "math.h"
 #include <string.h>
 
 static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
@@ -46,31 +47,50 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
 			prefix, RTLIL::unescape_id(module->name).c_str());
 }
 
-static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file)
+static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, std::string default_encoding)
 {
+	std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").str : "auto";
+
+	log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
+	if (encoding != "none" && encoding != "one-hot" && encoding != "binary") {
+		if (encoding != "auto")
+			log("  unkown encoding `%s': using auto (%s) instead.\n", encoding.c_str(), default_encoding.c_str());
+		encoding = default_encoding;
+	}
+
+	if (encoding == "none") {
+		log("  nothing to do for encoding `none'.\n");
+		return;
+	}
+
 	FsmData fsm_data;
 	fsm_data.copy_from_cell(cell);
 
-	log("Recoding FSM `%s' from module `%s':\n", cell->name.c_str(), module->name.c_str());
-
 	if (fm_set_fsm_file != NULL)
 		fm_set_fsm_print(cell, module, fsm_data, "r", fm_set_fsm_file);
 
-	fsm_data.state_bits = fsm_data.state_table.size();
+	if (encoding == "one-hot") {
-	if (fsm_data.reset_state >= 0)
+		fsm_data.state_bits = fsm_data.state_table.size();
-		fsm_data.state_bits--;
+	} else
+	if (encoding == "auto" || encoding == "binary") {
+		fsm_data.state_bits = ceil(log2(fsm_data.state_table.size()));
+	} else
+		log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
 	
-	int bit_pos = 0;
+	int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
-	for (size_t i = 0; i < fsm_data.state_table.size(); i++)
+	for (int i = 0; i < int(fsm_data.state_table.size()); i++)
 	{
+		int state_idx = fsm_data.reset_state == i ? 0 : state_idx_counter++;
 		RTLIL::Const new_code;
-		if (int(i) == fsm_data.reset_state)
+
-			new_code = RTLIL::Const(RTLIL::State::S0, fsm_data.state_bits);
+		if (encoding == "one-hot") {
-		else {
+			new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);
-			RTLIL::Const state_code(RTLIL::State::Sa, fsm_data.state_bits);
+			new_code.bits[state_idx] = RTLIL::State::S1;
-			state_code.bits[bit_pos++] = RTLIL::State::S1;
+		} else
-			new_code = state_code;
+		if (encoding == "auto" || encoding == "binary") {
-		}
+			new_code = RTLIL::Const(state_idx, fsm_data.state_bits);
+		} else
+			log_abort();
 
 		log("  %s -> %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
 		fsm_data.state_table[i] = new_code;
@@ -88,10 +108,12 @@ struct FsmRecodePass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    fsm_recode [-fm_set_fsm_file file] [selection]\n");
+		log("    fsm_recode [-encoding type] [-fm_set_fsm_file file] [selection]\n");
 		log("\n");
 		log("This pass reassign the state encodings for FSM cells. At the moment only\n");
-		log("one-hot encoding is supported.\n");
+		log("one-hot encoding and binary encoding is supported. The option -encoding\n");
+		log("can be used to specify the encoding scheme used for FSMs without the\n");
+		log("`fsm_encoding' attribute (or with the attribute set to `auto'.\n");
 		log("\n");
 		log("The option -fm_set_fsm_file can be used to generate a file containing the\n");
 		log("mapping from old to new FSM encoding in form of Synopsys Formality set_fsm_*\n");
@@ -101,6 +123,7 @@ struct FsmRecodePass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		FILE *fm_set_fsm_file = NULL;
+		std::string default_encoding = "one-hot";
 
 		log_header("Executing FSM_RECODE pass (re-assigning FSM state encoding).\n");
 		size_t argidx;
@@ -112,6 +135,10 @@ struct FsmRecodePass : public Pass {
 					log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
 				continue;
 			}
+			if (arg == "-encoding" && argidx+1 < args.size() && fm_set_fsm_file == NULL) {
+				default_encoding = args[++argidx];
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -120,7 +147,7 @@ struct FsmRecodePass : public Pass {
 			if (design->selected(mod_it.second))
 				for (auto &cell_it : mod_it.second->cells)
 					if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
-						fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file);
+						fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, default_encoding);
 
 		if (fm_set_fsm_file != NULL)
 			fclose(fm_set_fsm_file);