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https://github.com/YosysHQ/yosys
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sim -vcd: add date, version, and option for timescale
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4c925a3214
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@ -633,6 +633,7 @@ struct SimWorker : SimShared
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SimInstance *top = nullptr;
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SimInstance *top = nullptr;
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std::ofstream vcdfile;
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std::ofstream vcdfile;
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pool<IdString> clock, clockn, reset, resetn;
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pool<IdString> clock, clockn, reset, resetn;
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std::string timescale;
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~SimWorker()
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~SimWorker()
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{
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{
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@ -644,6 +645,15 @@ struct SimWorker : SimShared
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if (!vcdfile.is_open())
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if (!vcdfile.is_open())
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return;
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return;
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vcdfile << stringf("$version %s $end\n", yosys_version_str);
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vcdfile << stringf("$date ");
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std::time_t t = std::time(nullptr);
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vcdfile << std::put_time(std::localtime(&t), "%c %Z");
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vcdfile << stringf(" $end\n");
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if (!timescale.empty())
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vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
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int id = 1;
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int id = 1;
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top->write_vcd_header(vcdfile, id);
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top->write_vcd_header(vcdfile, id);
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@ -783,6 +793,9 @@ struct SimPass : public Pass {
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log(" -zinit\n");
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log(" -zinit\n");
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log(" zero-initialize all uninitialized regs and memories\n");
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log(" zero-initialize all uninitialized regs and memories\n");
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log("\n");
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log("\n");
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log(" -timescale <string>\n");
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log(" include the specified timescale declaration in the vcd\n");
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log("\n");
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log(" -n <integer>\n");
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log(" -n <integer>\n");
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log(" number of cycles to simulate (default: 20)\n");
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log(" number of cycles to simulate (default: 20)\n");
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log("\n");
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log("\n");
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@ -833,6 +846,10 @@ struct SimPass : public Pass {
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worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
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worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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continue;
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}
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}
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if (args[argidx] == "-timescale" && argidx+1 < args.size()) {
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worker.timescale = args[++argidx];
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continue;
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}
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if (args[argidx] == "-a") {
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if (args[argidx] == "-a") {
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worker.hide_internal = false;
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worker.hide_internal = false;
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continue;
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continue;
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