3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00

sim -vcd: add date, version, and option for timescale

This commit is contained in:
N. Engelhardt 2020-10-16 18:19:58 +02:00
parent 4c925a3214
commit 668d5253a5

View file

@ -633,6 +633,7 @@ struct SimWorker : SimShared
SimInstance *top = nullptr; SimInstance *top = nullptr;
std::ofstream vcdfile; std::ofstream vcdfile;
pool<IdString> clock, clockn, reset, resetn; pool<IdString> clock, clockn, reset, resetn;
std::string timescale;
~SimWorker() ~SimWorker()
{ {
@ -644,6 +645,15 @@ struct SimWorker : SimShared
if (!vcdfile.is_open()) if (!vcdfile.is_open())
return; return;
vcdfile << stringf("$version %s $end\n", yosys_version_str);
vcdfile << stringf("$date ");
std::time_t t = std::time(nullptr);
vcdfile << std::put_time(std::localtime(&t), "%c %Z");
vcdfile << stringf(" $end\n");
if (!timescale.empty())
vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
int id = 1; int id = 1;
top->write_vcd_header(vcdfile, id); top->write_vcd_header(vcdfile, id);
@ -783,6 +793,9 @@ struct SimPass : public Pass {
log(" -zinit\n"); log(" -zinit\n");
log(" zero-initialize all uninitialized regs and memories\n"); log(" zero-initialize all uninitialized regs and memories\n");
log("\n"); log("\n");
log(" -timescale <string>\n");
log(" include the specified timescale declaration in the vcd\n");
log("\n");
log(" -n <integer>\n"); log(" -n <integer>\n");
log(" number of cycles to simulate (default: 20)\n"); log(" number of cycles to simulate (default: 20)\n");
log("\n"); log("\n");
@ -833,6 +846,10 @@ struct SimPass : public Pass {
worker.resetn.insert(RTLIL::escape_id(args[++argidx])); worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
continue; continue;
} }
if (args[argidx] == "-timescale" && argidx+1 < args.size()) {
worker.timescale = args[++argidx];
continue;
}
if (args[argidx] == "-a") { if (args[argidx] == "-a") {
worker.hide_internal = false; worker.hide_internal = false;
continue; continue;