mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

RST -> RSTBRST for RAMB8BWER

Browse source
This commit is contained in:
Eddie Hung 2019-07-29 16:05:44 -07:00
parent b4f38cca77
commit 66806085db
1 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/xilinx/xc6s_brams_map.v
View file

@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
.CLKBRDCLK(CLK2 ^ !CLKPOL2), .CLKBRDCLK(CLK2 ^ !CLKPOL2),
.ENBRDEN(A1EN), .ENBRDEN(A1EN),
.REGCEBREGCE(|1), .REGCEBREGCE(|1),
.RSTB(|0) .RSTBRST(|0)
); );
endmodule endmodule
@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
.CLKBRDCLK(CLK3 ^ !CLKPOL3), .CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1), .ENBRDEN(|1),
.REGCEBREGCE(|0), .REGCEBREGCE(|0),
.RSTB(|0), .RSTBRST(|0),
.WEBWEU(B1EN_2) .WEBWEU(B1EN_2)
); );
end else begin end else begin
@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
.CLKBRDCLK(CLK3 ^ !CLKPOL3), .CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1), .ENBRDEN(|1),
.REGCEBREGCE(|0), .REGCEBREGCE(|0),
.RSTB(|0), .RSTBRST(|0),
.WEBWEU(B1EN_2) .WEBWEU(B1EN_2)
); );
end endgenerate end endgenerate