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https://github.com/YosysHQ/yosys
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Guard against sig mismatch
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parent
fd695c475b
commit
667a07ab56
2 changed files with 9 additions and 2 deletions
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@ -51,3 +51,5 @@ OBJS += passes/cmds/dft_tag.o
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OBJS += passes/cmds/future.o
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OBJS += passes/cmds/box_derive.o
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OBJS += passes/cmds/example_dt.o
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OBJS += passes/cmds/activity.o
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OBJS += passes/cmds/splitnetlist.o
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@ -77,8 +77,13 @@ struct ActivityProp {
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// Assign them to each SigBit (1 signal bit)
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for (int i = 0; i < GetSize(sig); i++) {
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SigBit bit(sig[i]);
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ActivityMap.emplace(bit, activities[i]);
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DutyMap.emplace(bit, duties[i]);
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if (i < activities.size() -1) {
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ActivityMap.emplace(bit, activities[i]);
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DutyMap.emplace(bit, duties[i]);
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} else {
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ActivityMap.emplace(bit, "0.0");
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DutyMap.emplace(bit, "0.0");
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}
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}
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}
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// Attach port activity to cell using sigmap
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