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Using worker class in memory_map

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This commit is contained in:
Clifford Wolf 2014-08-30 17:39:08 +02:00
parent eb571cba6a
commit 66763fad4e
1 changed files with 248 additions and 243 deletions
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25
passes/memory/memory_map.cc
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@ -23,7 +23,12 @@
#include <set>
#include <stdlib.h>
static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
struct MemoryMapWorker
{
RTLIL::Design *design;
RTLIL::Module *module;
std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
{
std::stringstream sstr;
sstr << "$memory" << name.str() << token1;
@ -45,7 +50,7 @@ static std::string genid(RTLIL::IdString name, std::string token1 = "", int i =
return sstr.str();
}
static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
void handle_cell(RTLIL::Cell *cell)
{
std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map;
@ -291,15 +296,16 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
module->remove(cell);
}
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module)
{
std::vector<RTLIL::Cell*> cells;
for (auto &it : module->cells_)
if (it.second->type == "$mem" && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : module->selected_cells())
if (cell->type == "$mem" && design->selected(module, cell))
cells.push_back(cell);
for (auto cell : cells)
handle_cell(module, cell);
handle_cell(cell);
}
};
struct MemoryMapPass : public Pass {
MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
@ -316,9 +322,8 @@ struct MemoryMapPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
handle_module(design, mod_it.second);
for (auto mod : design->selected_modules())
MemoryMapWorker(design, mod);
}
} MemoryMapPass;