diff --git a/tests/various/check_nolatches.ys b/tests/various/check_nolatches.ys
index 6dabf4b37..98ae07a26 100644
--- a/tests/various/check_nolatches.ys
+++ b/tests/various/check_nolatches.ys
@@ -1,7 +1,7 @@
 design -reset
 read_verilog <<EOT
-module top(input g, rn, d, output reg q);
-always @* if (~rn) q <= 0; else if (g) q <= d;
+module top(input g, d, output reg q);
+always @* if (g) q = d;
 endmodule
 EOT
 hierarchy -top top